EE
421L Digital Integrated Circuit Design - Lab 6
Design,
layout, and simulation of CMOS NAND/NOR/XOR gates and a full-adder
Pre-lab
work
- Back-up all of your
work from the lab and the course.
- Go through both Tutorial
4 and Electric_video_11
seen here.
- Read through the lab in its entirety before starting to work on it
- Draft the schematic of
a 2-input NAND gate (Fig. 12.1) using 10/2 MOSFETs (both NMOS and PMOS)
- Create layout and icon
views for this gate showing that the cells NCC, DRC, and well-check
without errors
- ensure that your icon
view is the commonly used symbol for a NAND gate (not a box!)
- ensure all layouts in
this lab use standard cell frames (sframe)
that snap together end-to-end for routing vdd
and gnd
- use an sframe height taller than you
need for these gates so that the same sframe
can be used for more complicated cells
- ensure gate inputs,
outputs, vdd, and gnd are all routed on metal1
- Use cell names that
include your initials and the current year/semester, e.g. NAND_jb_f19
(if it were fall 2019)
- Export, in the layout,
vdd, gnd, A, B, and the output ANANDB
- exports in the
schematic should not include vdd
or gnd
- Using both LTspice and
IRSIM simulate the logical operation of the gate for all 4 possible
inputs
- The following
statements may be useful when simulating the operation of a two-input
(inputs a and b) logic gate with LTspice
- Va a 0 pulse 5 0 0 1n 1n
2u 4u
- Vb b 0 pulse 5 0 0 1n 1n
1u 2u
- Your html lab report
should detail each of these efforts
- Repeat these steps for
a 2-input NOR gate using 20/2 PMOS devices and 10/2 NMOS devices
- Again, repeat these
steps for a 2-input XOR gate (Fig. 12.18) noting that the gate will
also need two inverters
- For all 12 transistors
used in the XOR gate use 20/2 PMOS and 10/2 NMOS devices
- Using these gates (and
3 inverters), draft the schematic of the full adder seen below
- Create an icon for
this full-adder (example)
- Simulate,
using LTspice and IRSIM, the operation of the
full-adder using this icon
- The following
statements may be useful when simulating the operation of the
full-adder with LTspice
- Va a 0 pulse 5 0 0 1n 1n
4u 8u
- Vb b 0 pulse 5 0 0 1n 1n
2u 4u
- Vcin cin 0 pulse 5 0 0 1n 1n
1u 2u
- Show how a full-adder
can be implemented using 3 NAND gates and 2 XOR gates
- Layout the full-adder
by placing the 5 gates end-to-end so that power and ground are routed
- full-adder inputs and
outputs can be on metal2 but not metal3
- NCC, DRC, and
well-check your full-adder layout
- Create another icon view and again simulate using LTspice and IRSIM
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cin |
s |
cout |
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As
always ensure that your html lab report includes your name and email
address
at the beginning of the report (the top of the webpage).
When finished backup your work (webpages
and design
directory).