Homework assignments and Project Information for EE 421 Digital Electronics and ECG 621 Digital Integrated Circuit Design, Fall 2023  

• Homework guidelines are found here.
• All simulations, schematics, and layouts should be done using Cadence. Using other tools will result in zero credit.
• Follow the instructions for running an Xterm found here (video).
• All problems are from the book.
• Unless otherwise indicated use the C5 process.
  

HW#19 – 14.7 but using the C5 process, due Monday, November 27  

HW#18 – 13.12, due Monday, November 20  

HW#17 – 12.8 but use a 2 pF load, due Wednesday, November 15    

HW#16 – design, layout, and simulate (using a symbol view of your oscillator) a 37-stage ring oscillator using C5 giving a comparison between your hand calculations and simulation results. Also design, layout, and simulate (using a symbol view of your NAND gate) a 2-input NAND gate using 10/1 devices in C5 (again, 10/1 = 6u/600n), due Wednesday, November 8

HW#15 – 11.11, 11.12, but using the C5 process. Also, design, layout, and simulate a buffer in the C5 process that uses a 24/12 inverter (minimum lengths) on its input that can drive 10 pF with a reasonable delay (discuss the design and associated trade-offs, use symbol views, that is, don't use transistor views in your simulations), due Monday, November 6   

HW#14 – 10.6, 10.7, and 10.9 but using the C5 process (30/1 = 18u/600n), due Monday, October 30

HW#13 - A bandgap reference circuit is a circuit that generates a reference voltage that doesn't vary (much) with changes in power supply voltage and temperature. For the course projects we'll use the bandgap circuit, designed for the C5 process, found in bandgap.zip (right-click to save as and then you may have to select "keep" for it to download).  For HW#13, run the simulations found in this design directory and comment to show that you understand what the simulations show, that is, the circuit's limitations (e.g., how low can the power supply go before the bandgap output voltage drops? how much does the reference voltage change with temperature? how does the diode's voltage change with temperature, how much current does the bandgap circuit draw?, etc.). Turn in these simulation plots with comments at the beginning of class on Monday, October 23. (Do not try to simulate the extracted layouts. The parasitic diodes don't extract properly.) In addition to this, lay out the bandgap reference circuit, again, for use in your course projects, making sure that your layout DRCs and LVSs without errors. Email your zipped–up bandgap directory (don't change the name, that is, it should still be "bandgap.zip"), now with the layout of the bandgap, to the course TA for grading (so he can determine if your layout DRCs and LVSs) before the beginning of class on Monday, October 23.

HW#12 – 6.21, 6.24, 6.29, and 6.31, due Wednesday, October 11   

HW#11 – 6.1 (but use a 200k resistor), 6.14, 6.17 and layout a 10k resistor using the hi-res layer in C5, DRC and LVS your layout, due Monday, October 9  
HW#10 – 5.8, 5.19, and layout a 1.25 pF poly-poly capacitor, DRC and LVS your layout, due Wednesday, October 4   
HW#9 – 5.7, 5.10, and layout a 60u/0.6u NMOS device using 10 fingers, DRC your layout, due Monday, October 2

HW#8 – 4.14, 4.16, layout a 6u/0.9u PMOS device in the C5 process, and sketch cross-sectional views (at least 3 at various locations) of your layout, due Wednesday, September 27
HW#7 – 3.21, 4.14, layout a 6u/0.9u NMOS device in the C5 process (see Tutorial 2), and sketch cross-sectional views (at least 3 at various locations) of your layout, due Monday, September 25

HW#6 – 3.15 and 3.16, due Wednesday, September 20
HW#5 – 3.8, 3.13, and 3.19 (see Tutorial 6) DRC your layout, due Monday, September 18

HW#4 – 2.1, 2.16, and 2.21, due Wednesday, September 13 

HW#3 – design, layout, and simulate (see Tutorial 1) a 1/4 voltage divider using four 8k n-well resistors in the C5 process (turn in screen shots of your schematic, symbol, simulation using the symbol, and your layout showing that it is DRC and LVS clean), due Monday, September 11

HW#2 – 1.16 and 1.23 (change peak amplitude to 2.5V), due Wednesday, September 6 

HW#1 – 1.13-1.14 (change the 5uA to -2uA), and 1.15, due Wednesday, August 30

Course projects – These projects are NOT group efforts. What you turn in should be your own work. 

Your project report, 10 pages maximum with 11 point type minimum, should detail:

• The reasons for the topology you selected including design considerations
• Hand calculations, where possible, with comparisons to simulations 
• A pin diagram for the design's layout (how to connect the layout to bond pads if we fabricate the design)
• Clear layout documentation (zoomed in and outlines of the layout for easy grading).
• Layout should be easy to understand (orderly and labeled). While tight layouts are desirable it's more important to provide clear layouts.
• Email me your (*clean*) zipped–up design directory (that I can place in my CMOSedu directory) file and project report in PDF format.
• I should be able to figure out what to simulate and how to simulate it without any effort (make sure this is very clear!) 
• I’ll perform an LVS and a DRC on what you send (so make sure everything is clean before emailing me!)
• One common error, that will make you lose a larger number of points, is sending me a directory that isn't self–contained, that is, references a cell in some other directory in your account (that I obviously don't have access to) so I can't simulate your design. 
• I should receive the electronic report and zipped–up directory of your design via email (r.jacob.baker@unlv.edu) prior to the beginning of class (4 pm) on Monday, December 4, 2023.
  

EE 421/ECG 621 project – The course project is to design a CMOS switching power supply, a synchronous Buck converter, that is powered with a VDD that can vary from 4 to 5.5 V. The power supply uses an off–chip inductor and capacitor to generate a constant output voltage of 3.125 V, which we'll call Vout below, for load currents ranging from 0 to 50 mA. 

1. In bandgap.zip is a bandgap voltage reference schematic designed for the C5 process. A bandgap is a common circuit used for generating a voltage reference of approximately 1.25 V that doesn’t change [much] with temperature and VDD variations. The first part of this project is lay out this bandgap. You shold have already done this in HW#13. Note that I’ve already laid out the parasitic pnp device (the diode) and there are example layouts, for LVSing, in this zip file. 
2. The second part of the project is to design a circuit that senses an input voltage Vin (this input is connected to the output voltage of the power supply, Vout, for feedback and control). Your design should use the bandgap from part 1. The output (called Enable) of the circuit is a logic 1 (vdd) when Vin is greater than 3.125 V and a logic 0 (ground) when Vin is less than 3.125 V. The circuit’s input, Vin, should draw no more than 50 uA of current and no less than 10 uA of current.  A practical design concern pops–up when Vin is near 3.125 V, which it will be in these projects. What will happen, if the circuit isn't designed correctly, is that the signal Enable will oscillate since Vin is moving slightly above and below 3.125 V. To avoid these oscillations, design your circuit with a small amount of hysteresis.  
• Hysteresis is found in a thermostat controlling your home’s A/C. If you have your thermostat set at 78 degrees your A/C may kick on when the temperature gets to 79 and then shut off when the house cools down to 77 (2 degrees of hysteresis). This keeps the A/C from cycling on and off and thus avoids high–frequency oscillations.
• You need to make an engineering design decision on how much hysteresis is appropriate. You'll see that too much will result in Vin (connected to Vout) varying too much. Too little hysteresis will result in high–frequency oscillations and poor efficiency. Note that you will be able to implement hysteresis by adding delay to the output of this sensing circuit, but hysteresis due to delay won't show up in a DC simulation. You'll see it in a transient simulation.
• Your report, among other things, should show DC sweeps (Vin v. Enable), with varying temperature/VDD, the performance of your design, again with varying temperature/VDD, using transient simulations (not DC simulations). Your design considerations (trade–offs), as mentioned above, should also be concisely detailed. 
• Note that your overall design can't be simulated using a DC simulation because, for proper operation, the output must be switching (hence the name "switching regulator") which can't occur in a DC sweep. Also note that you will likely have to set the output voltage, that is Vout, initial condition to 0. See why and how it was done in Tutorial 5 for ring oscillator so that the feedback circuit oscillates and works properly (in a real circuit noise starts the oscillations, in a simulation we have to help the oscillations start).
  
3. Use your design from part 2, that is, using Enable, to drive buffers (inverters) that enable/disable a PMOS switch connected between VDD and cell's output, out, and an NMOS switch connected between the cell's output, out, and ground. Your report, among other items, should discuss your thoughts on device sizing. Ensure the buffer you design has a lock–out feature, see Fig. 14.9, to ensure that the PMOS and NMOS are never on at the same time to avoid cross–over current.
4. The CMOS synchronous Buck switching power supply you are designing will be connected in 4 places: VDD, gnd, out, and Vout. What you LVS and DRC will be this cell; however, you will need to simulate this cell (generate a symbol view of your final design having 4 pins, or 2 pins if using global vdd! and gnd!) with the off–chip inductor and capacitor (the inductor and capacitor are not part of what we send out for fabrication). The output of your design, out, is connected to the inductor. The other side of the inductor is connected to Vout (the inductor is connected between out and Vout). The capacitor is connected from Vout to ground. Your report should detail your selection of the inductor and capacitor along with simulation results showing performance with varying temperature and power supply (plot your design's efficiency vs load current with different temperatures and power supply voltages). Of course, again, you need to also provide the details indicated above.  Note that efficiency, E, can be calculated using E = (Vout * Iload)/(VDD * AVG(I(VDD))) where AVG(I(VDD)) is the average (see page 4 here) current flowing the power supply, VDD.
• This efficiency calculation assumes that Vout, VDD, and Iload are DC values. Make sure only steady-state (no start-up waveforms) are present in I(VDD) when you use the calculator to calculate the average else your calculations will be incorrect. For example, to ensure that no start-up waveforms are present in the waveforms you may use .tran 50u 200u (a 200u simulation that starts saving data at 50u, again an example).
5. For students in ECG 621 your design should be able to supply up to 100 mA of current to a load.
   

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