Homework assignments and Project Information for EE 421 Digital Electronics and ECG 621 Digital Integrated Circuit Design, Fall 2015

• Homework guidelines are found here.
• Note that an A in front of the problem indicates an additional problem from the book’s webpage, not a problem from the book’s end–of–chapter problems.
• All simulations, schematics, and layouts should be done using Cadence. Using other tools will result in zero credit.
• Follow the instructions for running an Xterm found here (video)

HW#22 – A12.3, due Wednesday, November 25

HW#21 – A11.3, due Monday, November 23

HW#20 – A13.1–A13.3, due Wednesday, November 18  

HW#19 – A12.1, due Monday, November 16

HW#18 – A11.10, A11.11, and generate, using the C5 process, the schematic, symbol, layout and then show DC transfer curves and transient behavior of a 120u/60u inverter using a minimum L of 600 nm (use 10 fingers (M = 10) for each transistor), due Monday, November 9

HW#17 – Use the C5 process with VDD = 5 V for the following problems. Estimate the delay and compare to simulations: 1) a 6u/.6u NMOS discharging a 1 pF load, 2) a 12u/.6u PMOS charging a 1 pF load, 3) a 12u/6u inverter driving a 100 fF load, 4) a 12u/6u inverter driving another 12u/6u inverter, and 5) the delay through two 12u/6u inverters driving a 250 fF load, due Wednesday, November 4 

HW#16 – Layout the bandgap reference used in the project discussed below. Make sure your layout DRCs and LVSs without errors. Email your zipped up proj_rjb (last two or three letters are your initials) directory to the course TA for grading before the beginning of class on Wednesday, October 28.  

HW#15 – A11.1 and A11.2 (but with both resistors' values changed to 40k), draw the schematic, symbol, and layout (show your LVS has no errors) of a 12u/6u CMOS inverter (length = 0.6u) in the C5 process, and plot the voltage transfer curves (Vout vs. Vin) for this inverter using Spectre, due Monday, October 26  
HW#14 – A10.3 and A10.5, due Wednesday, October 21  
HW#13 – A10.1 and A10.2, due Monday, October 19 
HW#12 – A6.7–A6.10, due Wednesday, October 7  
HW#11 – A6.3–A6.6, due Monday, October 5
HW#10 – layout a 1 pF poly–poly capacitor using the C5 process. DRC and LVS your cells. Then do problem A5.10. Due Wednesday, September 30
HW#9 – layout a 10k poly2 (elec) resistor using the hi–res mask (to block the doping of poly2 so it's sheet resistance is high). Using the LVS tool, determine the sheet resistance of hi–res poly2. Then do problems A4.2 and A5.1. As always, DRC your layout. Due Monday, September 28
HW#8 – 1) layout a 6u/6u PMOS device connected to 4 bond pads. Show the cross–sectional view of the PMOS device similar to what is seen in Fig. 4.13 in the textbook (indicate where you are taking the cross–sectional view by drawing a line on your layout). 2) Estimate the delay through a length of polysilicon that is 100 nm wide and 1 mm long if the poly's sheet resistance is 1 ohm/square and it is periodically loaded with 100 fF capacitive loads every 2 um (500 capacitive loads). Verify your hand calculated answer with Spectre. Due Wednesday, September 23
HW#7 – A3.10, A4.1, A4.4, A4.5, and layout a 6u/6u (= W/L) NMOS device connected to 4 bond pads. DRC and LVS your layouts (see Tutorial 2 and Tutorial 6). Due Monday, September 21
HW#6 – A3.3, A3.8, and layout a 40 pad padframe that is roughly 1.5 mm x 1.5 mm using the pad from HW#5. Show a schematic and symbol for the padframe. Again, see Tutorial 6 and, again, as always, your layout should be DRC clean. Due Wednesday, September 16
HW#5 – A3.1 but using a scale (lambda) of 300 nm as in the C5 process, A3.2, and layout a bonding pad that is 75 um square (see first part of Tutorial 6). Note that you should show your bond pad DRCs without errors. Show a schematic and symbol for the bond pad. Due Monday, September 14
HW#4 – A2.12–A2.13, and then design, lay out (using n–well resistors), and simulate the operation of an attenuator circuit that takes a 0 to 5 V input signal and generates outputs of 0 to 1 V and 0 to 3 V (e.g., when the input is 5 V one output is 1 V and the other output is 3 V, when the input is 2.5 V one output is 0.5 V and the other output is 1.5 V, etc.). Your design should ensure that the input supplies no more than 100 uA of current (verify this and the general operation with simulations). Also comment on any differences between simulating the schematic and extracted layout (the input current will be slightly different but, if you design the circuit correctly the outputs, because of the ratio of resistances, should be the same). Due Wednesday, September 9
HW#3 – A2.1 and go through Cadence Tutorial 1 but use a 20k n–well resistor from the output to ground instead of 10k resistor as was used in the tutorial (so your circuit has one 10k resistor and one 20k resistor). Show, in a concise way, the following: a single simulation of sweeping the input from 0 to 1 V (see examples from Ch. 1 of the book for DC sweep such as seen in Fig. 1.16), the schematic, the layout, the symbol, and finally that there are no DRC or LVS errors. You should turn in no more than 4 sheets of paper that show your work and the HW questions. Due Wednesday, September 2
HW#2 – A1.15–A1.17, due Monday, August 31
HW#1 – hand calculate the output of the circuits in Figs. 1.22 and 1.31 of the book if all 3 resistors' values are changed from 1k to 2k. Verify your hand calculations using simulations. Make sure your hand calculations and comparisons are clear and concise (in other words follow the homework guidelines). Note that the purpose of this homework assignment is to ensure that you can run Cadence and follow the HW guidelines. Due Wednesday, August 26  

Course projects – Read the policy on the course webpage concerning turning in late work. These projects are NOT group efforts. What you turn in should be your own work. 

Your project report should detail:

• The reasons for the topology you selected including design considerations
• Hand calculations with comparisons to simulations 
• A pin diagram for the design's layout (how to connect the layout to bond pads if we fabricate the design)
• Clear layout documentation (zoomed in and outlines of the layout for easy grading).
• Layout should be easy to understand (orderly and labeled). While tight layouts are desirable it's more important to provide clear layouts.
• Email me your (*clean*) zipped–up design directory (that I can place in my CMOSedu directory) file and project report in PDF format.
• I should be able to figure out what to simulate and how to simulate it without any effort (make sure this is very clear!) 
• I’ll perform an LVS and a DRC on what you send (so make sure everything is clean before emailing me!)
• I should receive the electronic report and zipped–up directory of your design via email (r.jacob.baker@unlv.edu) prior to the beginning of class (4 pm) on Monday November 30, 2015. 

EE 421/ECG 621 project –

1. In bandgap.zip is a bandgap voltage reference schematic designed for the C5 process. A bandgap is a common circuit used for generating a voltage reference of approximately 1.25 V that doesn’t change [much] with temperature and VDD variations. Before beginning the project lay out this bandgap as mentioned above in HW#16. Note that I’ve already laid out the parasitic pnp device (the diode). 
2. The second part of the project is to design a circuit that senses an input voltage Vin (your design should use the bandgap from part 1 in this circuit). The output (called Enable) of the circuit is a logic 1 (vdd) when Vin is greater than –2.5 V and a logic 0 (ground) when Vin is less than –2.5 V. The circuit’s input, Vin, should draw no more than 50 uA of current and no less than 10 uA of current. The sensing circuit you design should have a built in hysteresis of at least 100 mV (but less than 200 mV). What this means, for 100 mV hysteresis, is that the output, Enable, of the circuit goes high when Vin goes above –2.45 V and then it goes low when the input goes below –2.55 V. 
• Hysteresis is found in a thermostat controlling your home’s A/C. If you have your thermostat set at 80 degrees your A/C may kick on when the temperature gets to 81 and then shut off when the house cools down to 79 (2 degrees of hysteresis). This keeps the A/C from cycling on and off. Characterize your design for VDD ranging from 4.5 to 5.5 V and for temperatures ranging from 0 to 100C. Note that your simulations should use a symbol of your total circuit (what you’ve designed and the bandgap reference) having 4 pins: vdd, gnd, Vin (the nominally –2.5 V signal), and Enable. If you use global vdd! and gnd! then a symbol with two pins, Vin and Enable, is okay.
3. Use your design from part 2 to enable a ring oscillator, using Enable, that drives buffers that drive a charge pump that supplies (nominally) –2.5 V with load currents ranging from 0 to 200 uA (the output of the charge pump is the input, Vin, in part 2). Again characterize your design for VDD ranging from 4.5 to 5.5 V and for temperatures ranging from 0 to 100C. The final cell that I simulate should have vdd and ground connections (or use global vdd! and gnd!) with a –2.5 V output voltage (in other words your final design should have a symbol view). Note that in Spectre you can model the load current with a current pulse. Show how robust your design is for varying load currents (say a pulse from 0 to 200 uA or from 200 uA to 0 etc.) Some thought is required to demonstrate, via simulations, a robust design. I would also like you to discuss the efficiency of the design. Ideally all of the power supplied by vdd, vdd*AVG(I(vdd)), is equal to the power delivered to the load, VLOAD*ILOAD (see page 4 here). In a real circuit this won’t be the case since your circuit will dissipate power.

• This efficiency calculation assumes that Vout, VDD, and Iload are DC values. Make sure only steady-state (no start-up waveforms) are present in I(VDD) when you use the calculator (see link below for help) to calculate the average else your calculations will be incorrect. For example, to ensure that no start-up waveforms are present in the waveforms you may use .tran 50u 200u (a 200u simulation that starts saving data at 50u, again an example).

4. For students taking ECG 621 increase the maximum load current specification from 200 uA to 1 mA.

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