EE 420L
Analog Integrated Circuit Design Laboratory
Laboratory Report 8: Characterization of the CD4007 CMOS transistor array.
AUTHOR: Henry Mesa
EMAIL: mesah1@unlv.nevada.edu
03-08-2020
Laboratory Overview: The goal to this laboratory is to use collected date from experiments to generate a Spice model. This model will allow users to conduct simulations that will follow the behavior of the MOSFETs used in this laboratory. CD4007model (Here you can find the model that was used to conduct the simulations in this laboratory. This model is the result generated from the collected data and hand calculations). 

 Due to laboratory restrictions set by Clark County School District to avoid the spread of Covid-19, experimental results in this laboratory are borrowed from student reports from previous semesters. Link to citations used in this laboratory are located at the end of this report.
Procedure: In this lab you will characterize the transistors in the CD4007 or the CD4007UB chips and generate SPICE Level=1 models. Assume that the MOSFETs will be used in the design of circuits powered by a single +5 V power supply. In other words, don't characterize the devices at higher than +5 V voltages or lower than ground potential.
  • Experimentally generate, for the NMOS device, plots of: 
    1. ID v. VGS (0 < VGS < 3 V) with VDS = 3 V 
    2. ID v. VDS (0 < VDS < 5 V) for VGS varying from 1 to 5 V in 1 V steps, and 
    3. ID v. VGS (0 < VGS < 5 V) with VDS = 5 V for VSB varying from 0 to 3 V in 1 V steps. 
  • Using your model simulate the delay of the inverter and compare to measured results. Adjust your SPICE model to get better matching between the experimental data and the measured data.
  • Repeat the above steps for the PMOS device where VDS, VGS, and VSB are replaced with VSD, VSG, and VBS respectively.
Experiment 1: ID v. VGS (0 < VGS < 3 V) with VDS = 3 V.

 
Hand Calculations to Detail Circuit's Operation:
 
 
Simulation:
 
 
Experimental Results:
 
  
Experiment 2: ID v. VDS (0 < VDS < 5 V) for VGS varying from 1 to 5 V in 1 V steps.

Simulation:
 
 
Experimental Results:
 
 
 
Experiment 3: ID v. VGS (0 < VGS < 5 V) with VDS = 5 V for VSB varying from 0 to 3 V in 1 V steps. 

 
Simulation:
 
 
Experimental Results:
 
 
Experiment 4: ID v. VSG (3 < VSG < 0 V) with VSD = 3 V.

 
Hand Calculations to Detail Circuit's Operation:
 
 
Simulation:
 
 
Experimental Results:
 
 
 
Experiment 5: ID v. VSD (5 < VSD < 0 V) for VSG varying from 1 to 5 V in 1 V steps.
 
Simulation:
 
 
Experimental Results:
 

 
 
Experiment 6: ID v. VSG (5 < VSG < 0 V) with VSD = 5 V for VSB varying from 0 to 3 V in 1 V steps. 
 
 
Simulation:
 
 
Experimental Results:
 

 
 
Experiment 7:

 
Simulation:
 

 
Experimental Results:
 
 
Comparing Hand Calculations, Simulation, and Experimental Results:
 
 
Works Cited:
  1. http://cmosedu.com/jbaker/courses/ee420L/s19/students/matacarl/Lab%208/Lab8.htm
  2. http://cmosedu.com/jbaker/courses/ee420L/s19/students/kerstett/lab_8/lab_8.htm
  3. http://cmosedu.com/jbaker/courses/ee420L/s19/students/mingura/lab_8/lab_8.htm
  4. http://cmosedu.com/jbaker/courses/ee420L/s19/students/sendad1/lab8/lab8.htm
  5. http://cmosedu.com/jbaker/courses/ee420L/s19/students/skellj1/lab8.htm
  

Return to index

Return to EE 420L Students

Return to EE 420L Spring 2020

Return to Dr. Baker's CMOSedu