EE 420L Engineering Electronics II Lab
Lab 8 - Characterization of the CD4007 CMOS transistor array
email: matacarl@unlv.nevada.edu
4/10/19
Pre-lab:
o
Review the datasheet for the CD4007.pdf CMOS
transistor array.
o
Ensure that you understand how the bodies of the NMOS are tied to
pin 7 (VSS, generally the lowest potential in the circuit, say ground) and that
the bodies of the PMOS are tied to pin 14 (VDD, generally the highest potential
in the circuit, say + 5V).
Lab
description:
The goal of this lab is to characterize the
transistors (MOSFETs) in the CD4007 chip and generate Spice 1 models. Which are
assumed to be used in circuit designs powered by +5V power supply.
Lab Requirements and conditions:
Experimentally generate, for the NMOS and PMOS
devices, plots of:
1.
ID v. VGS (0 < VGS < 3 V) with VDS = 3 V
2.
ID v. VDS (0 < VDS < 5 V) for VGS varying from 1 to 5 V in 1
V steps, and
3.
ID v. VGS (0 < VGS < 5 V) with VDS = 5 V for VSB varying
from 0 to 3 V in 1 V steps.
4.
Note that for this last one, if VSS (NMOS body) is ground
(again, the Body, VB, is grounded) then the source voltage will be varied from
0 to 3 V in 1 V steps to realize VSB ( = VS - VB = VS) varying from 0 to 3 V in
1 V steps. At the same time VGS will be varied from 0 to 3 V (when VS = 0), 1
to 4 V (when VS = 1 V), 2 to 5 V (when VS = 2 V), and 3 to 5 V (when VS =
3 V). In other words, as VS is increased by 1 V the VGS has
to shift up by 1 V as well.
5.
Assuming that the length of the NMOS is 5 um and its width is 500 um calculate the oxide thickness if Cox (= C'ox*W*L) = 5 pF.
6.
From this measured data create a Level = 1 MOSFET model with
(only) parameters: VTO, GAMMA, KP, LAMBDA, and TOX.
7.
Compare the experimentally measured data above (the 3 plots) to LTspice-generated data (again, 3 plots) and adjust your
model accordingly to get better matching.
8.
Experimentally, similar to what is seen on the datasheet (AC test
circuits seen on page 3 of the datasheet), measure the delay of an inverter
using these devices (remember the loading of the scope probe is around 15 pF
and there is other stray capacitance, say another 10 pF).
9.
Using your model simulate the delay of the inverter and compare to
measured results. Adjust your SPICE model to get better matching between the
experimental data and the measured data.
10.Repeat the above steps for
the PMOS device where VDS, VGS, and VSB are replaced with VSD, VSG, and VBS
respectively.
Characteristics of NMOS
1) ID v. VGS
(0 < VGS < 3 V) with VDS = 3 V
Values taken experimentally with plot shown
below
2. ID v. VDS
(0 < VDS < 5 V) for VGS varying from 1 to 5 V in 1 V steps
Plotting IV curve using Keithley
2450 SourceMeter
|
ID v. VDS (0 <
VDS < 5 V) VGS=1V |
|
|
ID v. VDS (0 <
VDS < 5 V) VGS=2V |
|
|
ID v. VDS (0 <
VDS < 5 V) VGS=3V |
|
|
ID v. VDS (0 <
VDS < 5 V) VGS=4V |
|
|
ID v. VDS (0 <
VDS < 5 V) VGS=5V |
|
3. ID v. VGS
(0 < VGS < 5 V) with VDS = 5 V for VSB varying from 0 to 3 V in 1 V
steps.
Values taken experimentally with plot
shown below
|
ID
v. VGS (0 < VGS < 5 V) VDS=5V VSB=0V
|
|
|
|
ID
v. VGS (0 < VGS < 5 V) VDS=5V VSB=1V |
|
|
|
ID
v. VGS (0 < VGS < 5 V) VDS=5V VSB=2V |
|
|
|
ID
v. VGS (0 < VGS < 5 V) VDS=5V VSB=3V |
|
|
Calculations:
Model parameters, NMOS
|
VT0=Vthn |
1.75V |
|
ID,sat |
565𝞵A |
|
KPn |
7.232𝞵A/V^2 |
|
Gamma, γ |
0.287 V^(1/2) |
|
Lambda, 𝞴 |
0.0257/V |
|
tox |
17.25nm |
After taking the hand calculated
values above and playing with different values to match the simulations, the
values below are being used to create the Level 1 models
Comparing experimental results with LTspice-generated data plots
|
Experimental |
LTspice |
|
ID v. VGS (0 < VGS
< 3 V) with VDS = 3 V
|
|
|
ID v. VDS (0 <
VDS < 5 V) for VGS varying from 1 to 5 V in 1 V steps
|
|
|
ID v. VGS (0 < VGS < 5 V) with
VDS = 5 V for VSB varying from 0 to 3 V in 1 V steps.
|
|
Characteristics of PMOS
11. ID v. VSG
(0 < VSG < 3 V) with VSD = 3 V
12.ID v. VSD (0 < VSD <
5 V) for VSG varying from 1 to 5 V in 1 V steps,
13.ID v. VSG (0 < VSG <
5 V) with VSD = 5 V for VBS varying from 0 to 3 V in 1 V steps.
4. ID v. VSG
(0 < VSG < 3 V) with VSD = 3 V
Values taken experimentally
with plot shown below
5. ID v. VSD
(0 < VSD < 5 V) for VSG varying from 1 to 5 V in 1 V steps,
Plotting IV curveS
using Keithley 2450 SourceMeter
|
ID v. VSD (0 < VSD
< 5 V) VSG=1V |
|
|
ID v. VSD (0 < VSD
< 5 V) VSG=2V |
|
|
ID v. VSD (0 < VSD
< 5 V) VSG=3V |
|
|
ID v. VSD (0 < VSD
< 5 V) VSG=4V |
|
|
ID v. VSD (0 < VSD
< 5 V) VSG=5V |
|
6.
ID v. VSG (0 < VSG <
5 V) with VSD = 5 V for VBS varying from 0 to 3 V in 1 V steps
Values taken experimentally with plot
shown below
|
ID
v. VSG (0 < VSG < 5 V) VSD=5V VBS=0V
|
|
|
|
ID
v. VSG (0 < VSG < 5 V) VSD=5V VBS=1V |
|
|
|
ID
v. VSG (0 < VSG < 5 V) VSD=5V VBS=2V |
|
|
|
ID
v. VSG (0 < VSG < 5 V) VSD=5V VBS=3V |
|
|
Calculations:
Model parameters, PMOS
|
VT0=Vthp |
1.7V |
|
ID,sat |
2.4mA |
|
KPp |
4.4𝞵A/V^2 |
|
Gamma,
γ |
0.287
V^(1/2) |
|
Lambda,
𝞴 |
0.0317/V |
|
tox |
17.25nm |
After taking the hand calculated
values above and playing with different values to match the simulations, the
values below are being used to create the Level 1 models
Comparing experimental results with LTspice-generated data plots
|
Experimental |
LTspice |
|
ID v. VSG (0 <
VGS < 3 V) with VSD = 3 V
|
|
|
ID v. VSD (0 < VSD
< 5 V) for VSG varying from 1 to 5 V in 1 V steps
|
|
|
ID v. VSG (0 < VSG < 5 V) with
VSD = 5 V for VBS varying from 0 to 3 V in 1 V steps.
|
|
CMOS Inverter
|
LTspice simulation |
Experimental
result |
|
|
|
|
|
|
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