EE 421L Final Project
Isabella Paperno
paperi1@unlv.nevada.edu
Project Task:
NOT A GROUP EFFORT
Design
a non-inverting buffer circuit that presents less than 100fF input
capacitance to on-chip logic and that can drive up to a 1pF (originally
10pF) load with output voltages greater than 7V (an output logic 0 is
near ground and an output logic 1 is greater than 7V). Assume VDD is
between 4.5V and 5.5V, a valid input logic 0 is 1V or less, a valid
input logic 1 is 3V or more. Show that your design works with varying
load capacitance from 0 to 1pF. Assume the slowest transition time
allowed is 4ns.
Part 1: Schematics and Simulations
First
half of the project (schematics and design discussions) and an html
report detailing operation (including simulations) is due Nov. 22.
Put the report (proj_pt1.html) in a folder called /proj in your directory at CMOSedu and link to your index.htm page.
Dr. Baker will go over the design in person, including running simulations, when lab meets on Nov. 22.
The report should detail the design details (why the specific topology and sizes were selected) as well as simulations.
Part 2: Layout and Documentation
Second half of the project, a verified layout and documentation (in html), is due Nov. 29.
Dr. Baker will meet with you on Nov. 29 to go over your layout and, again, put the report in the /proj folder in your CMOSedu.
Ensure there is a link on your project report webpage to your zipped design directory.
Complete Project
Combines both part 1 and part 2 into one document. Some adjustments were made to part 1 in order to condense the document.
Adjustments made include: adding more tables, removing graphs, adding images as clickable links in table
Return to EE421L Lab listings
Return to the directory listing of all Fall 2023 EE421L students
Return to Dr. Baker's EE 421L Fall 2023 webpage