Lab 1 - EE 421L Digital Integrated Circuit Design

Author: Matthew Meza

Email: mezam11@unlv.nevada.edu

August 31, 2015

  

Lab Intro, Lab Report, Cadence


 Pre-lab work
Lab Description
Lab Requirements

Tutorial Images


In order to create a schematic for simulation a Library must be made followed by a Cell.
Cadence has a very heirarchal system which helps keep projects organized.



Shown below is the resistive voltage divider schematic.  Notice that the two nodes (nets)
labeled "in" and "out" are highlighted. This means that they are chosen to be plotted in
the transient simulation. The voltage source, ground, and resistors were introduced into
the schematic by pressing "i" (instance) and selecting parts from the NCSU_Analog_Parts
folder.  
                    

The image below shows the transient response of the resistive voltage divider circuit shown above.
The voltage divider uses two 10K resistors which halfs the voltage. When simulating and plotting curves,
the line thickness can be adjusted by right clicking on the name (such as /out or /in) and clicking trace
properties. This is helpful if a snapshot of the curve must be taken for others to view.

 
 
Backup

All of my work done in EE421 Lab will be backed up via Onedrive. Onedrive will allow me to access
my work from my laptop and any other school computer if necessary. The image below shows the lab work
saved on my personal computer.



The image bleow shows the work being backed into Onedrive!




 

      

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