EE 421L Digital Integrated Circuit Design Laboratory
Fall 2014, University of Nevada, Las Vegas
Student lab reports are found here.
Current grades are located here.
Project – design, layout, and simulate an 8–bit ALU that can perform: A AND B, A OR B, A + B (addition), and A – B (subtraction).
First half of the project (no layout, just schematics and symbols), of your design and an html report detailing operation (including simulations), is due at the beginning of lab on Nov. 10.
The top level ALU symbol used for simulations should have the following inputs (all bus connections): A (8–bits), B (8–bits), F (2 bits), and Z (8–bits).
Ensure that you have input vectors saved (saved state) for simulations to show proper operation (make it easy to verify that your design works).
Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu.
Wenlan will go over your designs with you, including running simulations, when lab meets on Nov. 10.
Second half of the project, a verified layout and documention (in html), is due at the beginning of lab on Nov. 24.
Again, I will meet with you on Nov. 24 to go over your layout and, again, put your report in the /proj folder in your directory at CMOSedu.
Ensure that there is a link on your project report webpage to your zipped design directory.
Finishing the projects by Nov. 24 will give us time to assemble chips for fabrication through MOSIS.
Instructor: R. Jacob Baker
Lab Assistant: Wenlan Wu (see office hours at this link)
Time: Monday from 10:00 AM to 12:45 PM
Course dates: Monday, August 25 to Monday, December 1
Location: TBE B–350
Holidays: Monday, September 1 (Labor Day Recess)
Course content – Laboratory based analysis and design of digital and computer electronic systems.
Corequisite: EE 421; Prerequisite: EE 320L
40% Lab Reports