EE 421L Digital Integrated Circuit Design Laboratory
Fall 2014, University of Nevada, Las Vegas

 

Student lab reports are found here.

  

Current grades are located here.

 

Project – design, layout, and simulate an 8–bit ALU that can perform: A AND B, A OR B, A + B (addition), and A – B (subtraction).

First half of the project (no layout, just schematics and symbols), of your design and an html report detailing operation (including simulations), is due at the beginning of lab on Nov. 10. 

The top level ALU symbol used for simulations should have the following inputs (all bus connections): A (8–bits), B (8–bits),  F (2 bits), and Z (8–bits).

Ensure that you have input vectors saved (saved state) for simulations to show proper operation (make it easy to verify that your design works).

Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu.  

Wenlan will go over your designs with you, including running simulations, when lab meets on Nov. 10.

Second half of the project, a verified layout and documention (in html), is due at the beginning of lab on Nov. 24.

Again, I will meet with you on Nov. 24 to go over your layout and, again, put your report in the /proj folder in your directory at CMOSedu.  

Ensure that there is a link on your project report webpage to your zipped design directory.  

Finishing the projects by Nov. 24 will give us time to assemble chips for fabrication through MOSIS. 

 
November 24 – Lab8 – Generating a test chip layout for submission to MOSIS for fabrication, due December 1
October 20 – Lab7 – Using buses and arrays in the design of word inverters, muxes, and high–speed adders, due October 27
October 13 – Lab6 – Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder, due October 20
October 6 – Lab5 – Design, layout, and simulation of a CMOS inverter, due October 13  
September 29 – Lab4 – IV characteristics and layout of NMOS and PMOS devices in ON's C5 process, due October 6
September 22 – Lab3 – Layout of a 10–bit DAC, due September 29
September 8 – Lab2 – Design of a 10–bit digital–to–analog converter (DAC), due September 22
August 25 – Lab1 – Laboratory introduction, generating/posting html lab reports, due September 8
    

Instructor: R. Jacob Baker

Lab Assistant: Wenlan Wu (see office hours at this link)
Time: Monday from 10:00 AM to 12:45 PM

Course dates: Monday, August 25 to Monday, December 1

Location: TBE B–350

Holidays: Monday, September 1 (Labor Day Recess) 

Course content – Laboratory based analysis and design of digital and computer electronic systems.

Credits: 1

Corequisite: EE 421; Prerequisite: EE 320L

 

Grading
30% Quizzes
40% Lab Reports

30% Project
 

Policies 

  • Unlike the lectures, laptops can be used during the lab. Please bring your laptop with you to lab!
  • If a quiz is open book then only the course textbook can be used (no ebooks, Kindle, Nook, etc., older/international editions, or photocopies).
  • No late work accepted. Regularly being tardy for labs, leaving in the middle of labs, or leaving early is unacceptable without consent of the instructor.
  • Cheating or plagiarism will result in an automatic F grade in the lab
  • Questions for the instructor (only) should be asked in person (not via email).
  

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