EE 421L Digital Integrated Circuit Design - Lab 6

Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder

 

Pre-lab work



 l6f2.jpg l6f3.jpg l6f4.jpg l6f5.jpg l6f6.jpg  

  l6f7.jpg

   

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As always ensure that your html lab report includes your name and email address at the beginning of the report (the top of the webpage).
When finished backup your work (webpages and design directory).