EE 421 Digital
Electronics and ECG
621 Digital Integrated Circuit Design
Fall 2018, University
of Nevada, Las
Vegas
Course lecture
notes and videos are located here
Homework
assignments, due dates, and project information are located here
Current grades are located here.
Prior to the first day of class, but no earlier than one week before class starts, request an account on the Cadence servers as discussed here.
For the fabrication of chips in this class, On Semiconductor 500 nm, the C5 CMOS process with two polysilicon layers and 3 levels of metal.
The MOSIS scalable CMOS (SCMOS) are found in submicron design rules.
A MOSIS technology
code of SCN3ME_SUBM with a lambda of 300
nm is used with the design rules.
MOSIS information for this process is located here and the SPICE models are C5_models.txt
The Cadence examples from the lectures are found in C5_f18.zip (upload to, and unzip in, $HOME/CMOSedu)
Don't forget to add, to your cds.lib, DEFINE C5_f18 $HOME/CMOSedu/C5_f18 so the Library Manager sees the design directory
Textbook: CMOS Circuit
Design, Layout, and
Simulation, Third Edition (Chapters 1-6, 10-15)
Instructor: R. Jacob Baker (see office hours at
this link)
Teaching Assistant: Luis Soriano (office hours: Wednesdays 9-11 AM and Thursdays 1-3 PM, office location: TBE B-310)
Time:
MW 4:00 to 5:15 PM
Course dates: Monday, August 27 to Wednesday, December 5
Location: SEB-1243
Holidays: Monday, September 3 (Labor Day) and Monday, November 12 (Veterans Day)
Final exam time: Monday, December 10, 6 to 8 PM
Course content – An
introduction to the design, layout, and simulation of digital
integrated
circuits. MOSFET operation and parasitics. Digital design
fundamentals
including the design of digital logic blocks. Credits: 3
Prerequisites: CpE
100 and EE 320
Grading
25% Midterm
25% Homework/Quizzes
25%
Course Project (more complicated project for graduate credit, that is,
ECG 621)
25% Final
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