EE 421L Digital Integrated Circuit Design - Lab 4

IV characteristics and layout of NMOS and PMOS devices in ON's C5 process

 

Pre-lab work


 l4f1.jpg  l4f2.jpg  l4f3.jpg  l4f4.jpg  l4f8.jpg  l4f5.jpg  l4f6.jpg  l4f7.jpg

 

Ensure that your html lab report includes your name and email address at the beginning of the report (the top of the webpage).
When finished backup your work (webpages and design directory).