ECG 721 Memory Circuit Design
Fall 2018, University of Nevada, Las Vegas

Course lecture notes and videos are located here

Homework assignments, due dates, and project information are located here

Current grades are located here.

In this course we will make extensive use of LTspice.

Examples from the lectures are found in ecg721_f18.zip.  

Textbook: CMOS Circuit Design, Layout, and Simulation, Third Edition (Chapters 16-19) as well as handouts

Instructor: R. Jacob Baker (see office hours at this link)

Teaching Assistant: Eric Monahan

Time: offered as an online course to on-campus UNLV students

Course dates: Monday, August 27 to Wednesday, December 5

Location: offered as an online course to on-campus UNLV students

Holidays: Monday, September 3 (Labor Day) and Monday, November 12 (Veterans Day) 
Final exam time: TBA from TBA in TBA, open book and closed notes 

Course content – A practical introduction to the transistor-level design of memory circuits. Memory technologies including DRAM, Flash, MRAM, Glass-based, and SRAM will be discussed. 

Prerequisite EE 421 or ECG 621

Grading
25% Midterm 
25% Homework

25% Course Project
25% Final 

Course Policies

• No laptops or Internet appliances, such as smart phones, may be used during exams.
• Open book exams can use only the course textbook (no ebooks, PDFs etc., older/international editions, or photocopies).
• No late homework accepted. All assigned homework is due at 5 PM on the date it's due.
• The final exam will not be returned at the end of the semester, not even temporarily for you to review.
• Cheating or plagiarism will result in an automatic F grade in the course (so do your own homework and projects!)
• Email questions should be sent to the CMOSedu Google group (not directly to the instructor) at CMOSedu@googlegroups.com.
• Questions for the instructor (only) should be asked in person (not via email).

Course Outcomes

After completing ECG 721 students will be able to:

1. Discuss the difference between an open and closed DRAM array architecture

2. Design, for a DRAM, an n- and p-sense amplifier, row and column decoders, a data read/write path

3. Design a sigma-delta sensing circuit for a Flash memory

4. Design and simulate the operation of a charge pump for use in generating a voltage in a memory chip

5. Design and/or analyze an input buffer for a very-high speed data path

6. Design delay- and phase-locked loops for synchronization in high-speed memory chips

7. Discuss the concerns when designing high-speed DRAM memory chips including, the architecture limitations and how they relate to bandwidth, latency, and cycle time, data control, and power delivery  

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