Lab

Digital Integrated Circuit Design

EE 421L - Fall 2021

Lab 6

Author: Ryan Eclarinal

Email: eclarina@unlv.nevada.edu

Date Assigned: October 6, 2021

Due Date: October 20, 2021

Pre-Lab:

Go through Tutorial 4 .
In this tutorial, we were asked to draw the schematic, symbol and layout of a CMOS NAND gate.

First, we copy Tutorial 3 to a new library called Tutorial 4 in the Library Manager then we copy the
inverter cell to a new cell that we called "nand2".

Next is to draw the schematics of nand2.

We will then create a symbol for the schematic that we made.

Make sure to check and save your work.

The next thing that we need to do after creating the schematics and symbol is to simulate our design.
Here, we created another schematic for our simulation. Connect the pin A to vdd, connect a voltage source to pin B, and connect a capacitor to the ouput.

Setting the parameters:
Here, showing the parameters for the voltage source.

Make sure to setup the model library correctly. Add the following files for the simulation to work.

Setup the analog stimuli and put 5 DC voltage.

Were going to use the transient response.

Once everything is set, we are ready to run our simulation.

Here, showing the result of our simulation.

Close and save everything.

The next step is to design the layout for our NAND gate.

NAND gate Layout view and Extracted view.

Make sure to DRC your layout and to make sure that there is no error. If there is no error, we can now do the LVS.

Running the LVS showing the net-list matched

This ends the Tutorial 4.

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Lab 6 - Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder

Lab Procedure:

Draft the schematics of a 2-input NAND gate and a 2-input XOR gate using 6u/0.6u MOSFETs (both NMOS and PMOS)

Create layout and symbol views for these gates showing that the cells DRC and LVS without errors

ensure that your symbol views are the commonly used symbols (not boxes!) for these gates with your initials in the middle of the symbol
ensure all layouts in this lab use standard cell frames that snap together end-to-end for routing vdd! and gnd!
use a standard cell height taller than you need for these gates so that it can be used for more complicated layouts in the future
ensure gate inputs, outputs, vdd!, and gnd! are all routed on metal1

Use cell names that include your initials and the current year/semester, e.g. NAND_jb_f21 (if it were fall 2021)
Using Spectre simulate the logical operation of the gates for all 4 possible inputs (00, 01, 10, and 11)

comment on how timing of the input pulses can cause glitches in the output of a gate

Using these gates, draft the schematic of the full adder seen below

Create a symbol for this full-adder.
Simulate, using Spectre, the operation of the full-adder using this symbol

Layout the full-adder by placing the 5 gates end-to-end so that vdd! and gnd! are routed

DRC and LVS your full adder design

Experiment 1: 2-Input NAND Gate

Schematic of a 2-Input NAND gate:

Symbol for the NAND Gate:

Creating the Layout:

Extracted View:

LVS of the design showing the net -list matched

Simulation: Truth table of the NAND Gate

We will create a simple truth table by using a pulse source at the inputs.

Input A:

Input B:

Results of the simulation:

NAND Gate Truth Table:

It shows that the simulation results and the truth table matched.

We, also noticed that there were glitches in our output. To get this fix, we need to introduce more logic gates to the circuit for the output to stabilize the value. In this example,we used the inverter that we did in Lab 5.