EE 421L Digital Integrated Circuit Design Laboratory
Fall 2021, University of Nevada, Las Vegas

Student lab reports are found here.    

Current grades are located here.

Lab Chips

Chip1_f21 – Brian, Adrian, Joseph
Chip2_f21 – Jimmy, Kai, Ricardo
Chip3_f21 – David, Matthew, Mike   
Chip4_f21 – Luis, Michael, Charlene
Chip5_f21 – Brandon, Matthew, Tony
Chip6_f21 – David, Damian, Ryan    

Project (NOT a group effort) – design a register file (RF) that uses an 8-bit word and has 32 words. The RF uses a 5-bit 

address to access the 32 8-bit words. Other inputs to the RF are the 8-IO lines for reading and writing, a control signal, RW,

for indicating either a read or write to the RF, and VDD/ground.

First half of the project (schematics and design discussions) of your design and an html report detailing 

operation (including simulations), is due at the beginning of lab on Nov. 17.  

Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu and link to your index.htm page.  

Dr. Baker will go over your design with you (in person), including running simulations, when lab meets on Nov. 17.

Your report should show reading and writing to the RF at various addresses.

Second half of the project, a verified layout and documention (in html), is due at the beginning of lab on Nov. 24.

Dr. Baker will meet with you on Nov. 24 to go over your layout and, again, put your report in the /proj folder in your directory at CMOSedu.  

Ensure that there is a link on your project report webpage to your zipped design directory.  

November 24 – Lab8 – Generating a test chip layout for fabrication, due December 1
October 20 – Lab7 – Using buses and arrays in the design of word inverters, muxes, and high–speed adders, due November 3
October 6 – Lab6 – Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder, due October 20  
September 22 – Lab5 – Design, layout, and simulation of a CMOS inverter, due October 6  
September 15 – Lab4 – IV characteristics and layout of NMOS and PMOS devices in ON's C5 process, due September 22
September 8 – Lab3 – Layout of a 10–bit DAC, due September 15  
September 1 – Lab2 – Design of a 10–bit digital–to–analog converter (DAC), due September 8
August 25 – Lab1 – Laboratory introduction, generating/posting html lab reports, installing and using Cadence, due September 1  
Watch the Lab Safety Training video and review the Lab Rules & Regulations here

Instructor: R. Jacob Baker

Lab Assistant (grader): David Santiago (Office Hours: TBA, email to get access) 
Time: Wednesdays from 11:30 to 2:15 PM  

Course dates: Wednesday, August 25 to Wednesday, December 1

Location: TBE B–350  

Holidays: None

Course content – Laboratory based analysis and design of digital and computer electronic systems.

Credits: 1

Corequisite: EE 421; Prerequisite: EE 320L

Grading
30% Quizzes
40% Lab Reports

30% Project

Policies

• Unlike the lectures, laptops can be used during the lab. Please bring your laptop with you to lab!
• No late work accepted. Regularly being tardy for labs, leaving in the middle of labs, or leaving early is unacceptable without consent of the instructor.
• Cheating or plagiarism will result in an automatic F grade in the lab
• Email questions should be sent to the CMOSedu Google group (not directly to the instructor) at CMOSedu@googlegroups.com.
• Questions for the instructor (only) should be asked in person (not via email). Please talk to the instructor. Please don't email the instructor.

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