EE 421L Digital Integrated Circuit Design Laboratory
Fall 2020, University
of Nevada, Las
Vegas
Student lab reports are found here.
Current grades are located here.
Lab Chips
Project (not a group effort, each student will turn in their own project) – design, layout, and simulate a digital receiver circuit that accepts a
high-speed digital input signal D and Di (a differential pair connected to your circuit from, for example, a twisted pair of wires such as in an
Ethernet cable). D and Di are complements so, for example, if D is 5V then Di is 0V and output = 1. Another example, when D is 1V and Di is 2V
then output = 0. At high-speeds and long distances the voltages received aren't full digital logic levels (i.e., 5V and 0V), hence the need to design,
and use, a high-speed digital recevier circuit. Ideally, when D > Di the receiver outputs a 1. When D < Di the receiver outputs a 0. Base your
design on the topology seen in Fig. 18.23. Try to design for high-speed and low-power. Characterize your design (in sims) and the trade-offs.
For example, show that you get higher-speed if you use more energy (burn more power). See if you can get, in this 500 nm process, 250 Mbits/s
(a bit width of 4 ns) with an input voltage difference of, for example, 250 mV (with D and Di swinging back and forth between 2.75V and 3V,
for one of many examples, your circuit outputs the correspondingly correct values). Note that while Fig. 18.23 shows one inverter on the output
you may find, for example, that two inverters work better (at the cost of power). Use a table to summarize your design's performance.
First half of the project (schematics and design discussions) of your design and an html report detailing
operation (including simulations), is due at the beginning of lab on Nov. 18.
Your design report in html should show various input clock frequencies and VDD voltages to show it works.
Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu and link to your index.htm page.
Dr. Baker will go over your design with you (in person), including running simulations, when lab meets on Nov. 18.
Second half of the project, a verified layout and documention (in html), is due at the beginning of lab on Nov. 25.
Dr. Baker will meet with you on Nov. 25 to go over your layout and, again, put your report in the /proj folder in your directory at CMOSedu.
Ensure that there is a link on your project report webpage to your zipped design directory.
November 25 – Lab8 – Generating a test chip layout for submission to MOSIS for fabrication, due December 2
Instructor: R. Jacob Baker
Lab Assistant: James Skelly (Office Hours: Tuesdays and Thursdays, 8 -10 AM, email to get access)
Time: Wednesday from 11:30 to 2:15 PM
Course
dates: Wednesday, August 26 to Wednesday, December 2
Location: TBE B–350
Holidays: November 11, Veteran's Day
Course content – Laboratory
based analysis and design of digital and computer electronic systems.
Credits: 1
Corequisite: EE 421;
Prerequisite: EE 320L
Grading
30% Quizzes
40% Lab Reports
30% Project
Policies