Lab 8 - EE 421L Fall 2015

Chip 7


Authored by:

 

Luis A. Soriano,

sorian20@unlv.nevada.edu

 

Co Nguyen

nguyec3@unlv.nevada.edu

 

Mario De La Torre

delatm2@unlv.nevada.edu

11/30/2015 

Zip folder containing Chip7 files found here.


 

Pre-lab work

 

This tutorial is about placing the circuit from early tutorial into a padframe.
1. Create a pad 75 um.
 
http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab8/pre1_pad.JPG
 
2. Once the pad is created we can use it to layout padframe about 1.5mmX1.5mm.
 
Symbol
 
http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab8/pre2_padframe_symbol.JPG
 
Layout
 
http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab8/pre2_padframe.JPG
 
3.  Now we start with an schematic of all the components in the chip and assign the pins.
 
http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab8/pre3_chip_schematic.JPG

 
Layout and DRC.
 
http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab8/pre4_chip_layout.JPG
 
 
Extracted view.
   
http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab8/pre4_chip_extracted.JPG

LVS with no errors.
 
http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab8/pre4_chip_LVS.JPG
 
This concludes Tutorial 6.
 

Form into groups of 4 students that will put the test structures on the chip.
Each test circuit should have its own power but ground should be shared between the circuits.
Power should not be shared between the circuits so that a vdd!-gnd! short in one circuit doesn't make one of the other circuits inoperable.


Your chip should include the following test structures:

   The image seen at the bottom of the page shows how the chip's pads correspond to the pins of the 40 pin DIP package we'll receive from MOSIS.


http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab8/dip40.jpg
 
 
Chip Design
 
 
Pin NumberDescriptionNotes
1 Not used
2 Not used
3vdd(31-stage Ring Oscillator)+5 V
4Oscillator_Out(31-stage Ring Oscillator)
5Vout (Voltage divider)To meausere the 10k resistor use pin 5 and pin 6 with no vdd applied
6Vin (Voltage divider)To measuere the 25k resistor use pin 5 and pin 20.
7Q8(8 bit up/down counter) MSB
8Q7(8 bit up/down counter)
9Q6(8 bit up/down counter)
10Q5(8 bit up/down counter)
11Q4(8 bit up/down counter)
12Q3(8 bit up/down counter)
13Q2(8 bit up/down counter)
14Q1(8 bit up/down counter)LSB
15vdd (8 bit up/down counter)+5 V
16Clock in (8 bit up/down counter)
17Clear  (8 bit up/down counter)Clear=1 will  clear the counter
18Up/Down (8 bit up/down counter)1= Up count,  0=Down count
19Not used
20GROUND This pin is used as ground for all the circuits
21vdd (NAND GATE)+5 V
22A input (NAND GATE)
23B input (NAND GATE)
24 Output (NAND GATE)
25vdd (NOR GATE)+5 V
26B input (NOR GATE)
27A input (NOR GATE)
28Output (NOR GATE)
29Source (PMOS)
30Gate (PMOS)
31Drain (PMOS)
32Body (PMOS)
33Source (NMOS)
34Gate  (NMOS)
35Drain (NMOS)Note the body of the NMOS is grounded
36Not used
37Input (inverter)
38Output (inverter)
39vdd (inverter)+5 V
40VDD+5 V
 
 
The following is the final schematic of our chip.
 
http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab8/chip7_schematic.JPG

Test result click here

   

Full layout of the MOSIS chip

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab8/chip7_layout.JPG

 

 

 Full extract of the MOSIS chip

  

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab8/chip7_extract.JPG

 
 
DRC of MOSIS Chip


http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab8/chip7_DRC.JPG
     
 

LVS-no error- of MOSIS Chip

 

 http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab8/chip7_LVS1.JPG

 
 
Output of MOSIS Chip
 
 
http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab8/chip7_LVS2.JPG

  

Saving my work:

 

 

Zip files:

 

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