Lab 8 - ECE 421L
See the EE421L webpage here

Authored by Juan Buendia
buendiaj@unlv.nevada.edu
November 30, 2015

Objective: To generate a test chip layout for submission to MOSIS for fabrication.

We split into groups of four, and our group will fabricate chip #1.

Chip #1 Group Members:
Shada Shariff, Stephanie Silic, Jared Hayes, Juan Buendia

Pre-lab work:

• Back-up all of your work from the lab and the course.
• Go through Cadence Tutorial 6 seen here.
• Read through the lab in its entirety before starting to work on it

 
Lab Description:

• The lab is about generating a test chip layout that will be submitted to MOSIS for fabrication.

Lab Report will include:

• One up/down counter with clear
• The outputs of your counter should be buffered before connecting to a pad
• A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
• NAND and NOR gates using 6/0.6 NMOSs and PMOSs
• An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
• Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad) 
• Note that only one pad is need for the common gnd pad. This pad is used to ground the p-substrate and provide ground to each test circuit
• Using the 25k resistor laid out below and a 10k resistor implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor) 
• A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)  
• Analog padframe with all the parts mentioned above.
• Instructions for testing the chip.

Chip 1 Padframe:

• Contents include: Pmos, Nmos, Nand Gate, Nor Gate, 31-stagering oscillator, coltage divider, and an 8-bit resettable (clear) UP/DOWN counter
• Padframe is an analog padframe which provides ESD protection when VDD (pin 40) is applied
• Each component shares a global gnd, but each component has their own supply (they will not use a global vdd), and it will protect the other devices should one of them encounter a problem (such as a short).

Pad Frame Schematic


Pad Frame Layout



Pad Frame Extracted View



DRC



LVS



Pad Frame Pinout
The layout and the extracted views of the padframe do not do a good job of showing the numbering scheme of the chip, but it follows the same numbering scheme as the following picture:



This should be used as a reference when testing the chip out.

Testing Procedure:

• UP/DOWN 8-bit Counter
• The first thing to do before using the counter is to connect pin<8> to an external vdd so that the counter is powered.
• Our counter is able to count UP/DOWN depending in the UP_in, which is pin<9> signal provided, when UP_in is high the counter counts up, and when UP_in is low the counter counts down. 
• For the counting to start happening user should input a clock signal to pin<10> that is CLK. Looking at Project report user can understand how the counter functions.
• The CLEAR input is pin<11> and when it is high the output is cleared to 0, and when it is low the counter works as normal. 
• As for the 8 bit outputs we have 
• S<0> is from pin<15>
• S<1> is from pin<14>
• S<2> is from pin<13>
• S<3> is from pin<12>
• S<4> is from pin<7>
• S<5> is from pin<6>
• S<6> is from pin<5>
• S<7> is from pin<4>
• 31-Stage Ring Oscillator
• To power the ring oscillator connect vdd to a power supply and that is pin<24>.
• The output of the oscillator can be observed from pin<25>.
• The output of the oscillator has already been buffered on-chip so that the oscillator can handle a 20 pF off-chip load.
• The testing of the oscillator driving the 20 pF load can also be seen in Project report.
• NAND and NOR gates
• NAND and NOR gates share the same input pins that will be noted below.
• NAND
• To power the NAND gate connect pin<31> to a power supply.
• Input A is pin<28> and input B is pin<29>. 
• To measure the output use pin<30>.
• NOR
• To power the NOR gate connect pin<33> to a power supply. 
• Inputs A and B are again pin<28> and pin<29> respectively.
• The output is measured from pin<32>.
• Sample simulations for the nand and nor gates can be found in Project report, showing different inputs and the corresponding outputs. 

• Inverter
• To power the inverter's vdd connect pin<35> to a power supply.
• The input of the inverter is shared again from pin<29> that was used for the NAND and NOR gates.
• The output is measured from pin<34>.
• PMOS and NMOS
• PMOS
• The gate of the PMOS is connected to pin<17>.
• The source of the PMOS is connected to pin<16>.
• The drain of the PMOS is connected to pin<18>.
• The body of the PMOS is connected to pin<19>.
• In order to avoid body effects of the PMOS the body should be connected to vdd from the power supply. Otherwise, the characteristics of the PMOS will vary like the Vth voltage.
• NMOS
• The gate of the NMOS is connected to pin<23>.
• The source of the NMOS is connected to pin<22>.
• The drain of the NMOS is connected to pin<21>.
• The body of the NMOS is connected to pin<20> that is the ground pin, which should be connected to ground as instructed above before starting to test anything.
• Voltage divider, and resistors
• 25K resistor
• In order to test the 25k resistor connect one end of the multimeter to pin<36> and the other end to pin<37>. 
• Make sure ground pin<20> is connected to ground.
• 10K resistor
• Connect one end of the multimeter to pin<37> again and the other end to the ground pin<20>.
• Voltage divider
• Connecting pin<20> to ground.
• The input signal should be from pin<36>, and to measure the output connect the positive end of the multimeter or the scope to pin<37>  and the other end to the ground pin pin<20>.
• In the Project report a 5V signal was tested and the output was 1.43V.

Backup

As always I zipped my lab 8 folder and emailed it to myself for backup