EE 420L – Engineering Electronics II Lab – Lab 9 

Authored by James Skelly

Email: skellj1@unlv.nevada.edu

Due: April 24, 2019

  

 

Lab Description

·        Designing and implementing a Beta-Multiplier Reference using the CD4007 CMOS transistor array.

 

 

 

Pre-Lab

  • This lab will use the level=1 MOSFET model created in lab 8 and, again, the MOSFETs in the CD4007.pdf CMOS transistor array.
  • Design and simulate the operation of a BMR that biases the NMOS devices so that they have a gm of 20 uA/V 
    • Use a simple (big) resistor to VDD for the start-up circuit (explain how the addition of a resistor ensures start-up). 
      • When the BMR is operating the current in the big resistor should be much smaller than the current flowing in each branch of the BMR 
  • Write-up, similar to a homework assignment, your design calculations and simulation results. (This will count as the pre-lab quiz.)
  • Ensure that you show the following in what you turn in:
    • Hand calculations
    • Operation as VDD is swept from 0 to 10 V 
      • Vbiasn should stabilize (be constant) after VDD hits a minimum value (estimate this value of VDD assuming VGS/VSG is a threshold voltage and VDS,sat/VSD,sat is zero).
      • Vbiasp should follow VDD after VDD hits a minimum value (show this in simulations)
    • Unstable operation if too much capacitance is shunting the BMR's resistor (see bottom of page 630)
    • Comments comparing the hand calculations with the simulation results.

 

             CD4007 Chip

 

 

Lab Tasks

 

In this lab you may need to use two, or more, CD4007 chips from the same production lot (see date code on the top of chip) to ensure using a BMR to bias a current mirror is possible. If the CD4007 chips are not from the same production lot they will not "match" so current mirrors will not be possible.

 

  • Build your BMR design and characterize it as you did in the pre-lab (if you use two chips ensure that grounds and VDDs of both chips are tied together).
    • You expect the BMR to become unstable if there is a large capacitance across the resistor, such as a scope probe (important), so care must be exercised 
  • Use your BMR to bias, and thus create, a:
    • NMOS current mirror 
    • PMOS current mirror
  • Measure how the current varies through each current mirror as the voltage across the mirror changes.
    • Of course the current in the NMOS (PMOS) current mirror goes to zero as the voltage on the drain of the output device moves towards ground (VDD)
  • Using these current mirrors drive two gate-drain connected transistors
    • For the first experiment use the NMOS current mirror to drive two PMOS gate-drain connected devices. 
      • Use the voltages on the gate-drain connection of the two devices to bias a cascode current mirror (characterize this mirror as before)
    • For the second experiment switch, that is, use the PMOS current mirror to drive two NMOS gate-drain connected devices.
      • Again, use these two voltages to bias an NMOS cascode current mirror then characterize.

 

 

A spreadsheet containing the experimental data collected in this lab can be found here.

Calculations and simulations used to characterize the devices (from lab 8) can be found here.

 

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Spice Models Generated in Lab 8

 

 

 

 

The Beta-Multiplier Reference

 

A report (prelab) detailing the design of the BMR can be found here.
Hand calculations for the design (from the prelab) of the BMR can be found here.

 

 

 

Theoretical Steady-State Bias Voltages

 

 

The transient simulation above provides us with expected, theoretical bias voltages for the BMR.

We see in the first hundred milliseconds or so, the voltages are unstable. This is because the circuit is

starting up, and current is being injected into the drain of NMOS device M1 to get the circuit going.

 

From the plot:

                        Vbiasntheoretical = 1.633V

                        Vbiasptheoretical = 3.465V

 

 

 

Experimental Results

 

Experimental Vbiasn                   Experimental Vbiasp

  

 

Here, we see that the experimental values for bias voltages reasonably agree with the theoretical values.

 

 

Test Setup and Breadboard Implementation of BMR

 

 

 

 

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NMOS Current Mirror

 

The NMOS current mirror was implemented using two CD4007 transistor array chips with the same date code.

Thanks to this date code matching, our simulation results and experimental results are nearly identical, as we see that

once VDD reaches a minimum value, the current mirror snaps to a constant current of just less than 1.8 µA.  

 

Simulation Results

 

 

 

Experimental Results

 

 

 

The plot above (left) was generated using excel, and the plot above (right) was generated with the Kiethley source meter.

We see from experimentation that the spice models generated in lab 8 do a good job modeling the actual behavior of the transistor array

for the NMOS current mirror.

 

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PMOS Current Mirror

 

The PMOS current mirror was also implemented using two CD4007 transistor array chips with the same date code.

Our simulation results and experimental results agree in this experiment as well. We see from both theoretical simulations

that the current in the PMOS does not flow until the device turns on at the minimum VDD for this PMOS (VSG > VTHP).

 

Simulation Results

 

 

 

Experimental Results

 

 

 

The plot above (left) was generated using excel, and the plot above (right) was generated with the Kiethley source meter.

We see from experimentation that the spice models generated in lab 8 do a good job modeling the actual behavior of the transistor array

for the PMOS current mirror.

 

 

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NMOS Cascode Current Mirror

 

For the NMOS Cascode Current Mirror, the lab ran out of CD4007 chips, and we were forced to combine the transistors

we have been using and characterizing this whole time with the CD4007UBE transistor array chip, which is capable of sourcing

and sinking higher currents and operating with higher power supply voltages than the CD4007. For this reason, our spice simulations

for the Cascode Current Mirrors are off by a large factor as far as magnitude of current flow, but the overall shape of the curve

is identical.

 

Simulation Results

 

 

 

Experimental Results

 

 

 

As expected, the NMOS cascode current mirror has less noise and a much more stable current than the NMOS current

mirror excluding the cascode design. The purpose of the cascode is to introduce a much higher output resistance, as the large

output resistances of the devices are added together. Also, cascoding includes gate-drain connected devices, which always operate

in the saturation region.

 

 

----------------------------------------------------------------------------

 

 

PMOS Cascode Current Mirror

 

For the PMOS Cascode Current Mirror, we were also forced to use the CD4007UBE transistor array chip.  

As was mentioned previously, the CD4007UBE transistor array chip is capable of sourcingand sinking higher currents

and operating with higher power supply voltages than the CD4007. For this reason, our spice simulations for the Cascode

Current Mirrors are off by a large factor as far as magnitude of current flow, but the overall shape of the curve

is identical.

 

 

Simulation Results

 

 

 

Experimental Results

 

 

 

As expected, the PMOS cascode current mirror has less noise and a much more stable current than the PMOS current

mirror excluding the cascode design. The purpose of the cascode is to introduce a much higher output resistance, as the large

output resistances of the devices are added together. Also, cascoding includes gate-drain connected devices, which always operate

in the saturation region.

 

 

 

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