ECG 721 Memory Circuit Design
Spring 2020, University of Nevada, Las Vegas

Course lecture notes and videos are located here

Homework assignments, due dates, and project information are located here

Current grades are located here.

In this course we will make extensive use of LTspice.

Examples from the lectures are found in ecg721_s20.zip.  

Textbook: CMOS Circuit Design, Layout, and Simulation, Fourth Edition (Chapters 16-19) as well as handouts

Instructor: R. Jacob Baker (see office hours at this link)

Teaching Assistant (grader): James Skelly

Time: offered as an online course to on-campus UNLV students

Course dates: Wednesday, January 22 to Wednesday, May 6

Location: offered as an online course to on-campus UNLV students

Holidays: Monday, February 17 (Washington's Birthday), March 16 and 18 (Spring break from instruction)  
Final exam time: Monday, May 11 from 6 - 8 PM in SEB-1242, open book and closed notes 

Course content – A practical introduction to the transistor-level design of memory circuits. Memory technologies including DRAM, Flash, MRAM, Glass-based, and SRAM will be discussed. 

Prerequisite EE 421 or ECG 621

Grading
25% Midterm - Wednesday, March 25 from 5:30 to 6:45 PM in TBA, open book and closed notes
25% Homework

25% Course Project
25% Final - Monday, May 11 from 6 to 8 PM in SEB-1242, open book and closed notes

Course Policies

• No laptops or Internet appliances, such as smart phones, may be used during exams.
• Open book exams can use only the course textbook (no ebooks, PDFs etc., older/international editions, or photocopies).
• No late homework accepted. All assigned homework is due at 5 PM on the date it's due.
• The final exam will not be returned at the end of the semester, not even temporarily for you to review.
• Cheating or plagiarism will result in an automatic F grade in the course (so do your own homework and projects!)
• Email questions should be sent to the CMOSedu Google group at CMOSedu@googlegroups.com.

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