ECG 721 Memory Circuit Design
Spring 2017, University of Nevada, Las Vegas

 

Course lecture notes and videos are located here

Homework assignments, due dates, and project information are located here

 

Current grades are located here.

 

In this course we will make extensive use of LTspice.

Examples from the lectures are found in ecg721_s17.zip.  

  

Textbook: CMOS Circuit Design, Layout, and Simulation, Third Edition (Chapters 16-19) as well as handouts

Instructor: R. Jacob Baker (see office hours at this link)

Teaching Assistant: Shada Sharif  

Timeoffered as an online course to on-campus UNLV students

Course datesWednesday, January 18 to Wednesday, May 3

Locationoffered as an online course to on-campus UNLV students

HolidaysMonday, February 20 (Washington's Birthday), April 10 and 12 (Spring break from instruction)   
Final exam time: Monday,
May 8 from 6 - 8 PM in SEB-1240, open book and closed notes  

Course content  A practical introduction to the transistor-level design of memory circuits. Memory technologies including DRAM, Flash, MRAM, Glass-based, and SRAM will be discussed. 

Prerequisite EE 421 or ECG 621

 

Grading
25% Midterm - Wednesday, March 15 from 5:30 to 6:45 PM in SEB-1240, open book and closed notes
25% Homework

25% Course Project
25% Final - Monday, May 8 from 6 to 8 PM in SEB-1240, open book and closed notes
 

 

Course Policies

 

Course Outcomes 

After completing ECG 721 students will be able to:

1.     Discuss the difference between an open and closed DRAM array architecture

2.    Design, for a DRAM, an n- and p-sense amplifier, row and column decoders, a data read/write path

3.    Design a sigma-delta sensing circuit for a Flash memory

4.    Design and simulate the operation of a charge pump for use in generating a voltage in a memory chip

5.    Design and/or analyze an input buffer for a very-high speed data path

6.    Design delay- and phase-locked loops for synchronization in high-speed memory chips

7.   Discuss the concerns when designing high-speed DRAM memory chips including, the architecture limitations and how they relate to bandwidth, latency, and cycle time, data control, and power delivery  

   

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