ECG 721 Memory
Circuit Design
Fall 2015, University of Nevada, Las
Vegas
Course lecture
notes and videos are located here
Homework
assignments, due dates, and project information are located here
Current
grades are located here.
In this course we will make extensive use of LTspice.
Examples from the lectures are found in ecg721_f15.zip.
Textbook: CMOS Circuit Design, Layout, and Simulation, Third Edition (Chapters 16-19) as well as handouts
Instructor: R. Jacob Baker (see office hours at this link)
Time: MW 2:30 to 3:45 PM
Course
dates: Monday, August
24 to Wednesday, December 2
Location: TBE B-309
Holidays: Monday, September 7 (Labor Day Recess)
and Wednesday, Nov. 11 Veteran's Day Recess
Final exam time: Wednesday, Dec. 9, 3:10 to 5:10 PM
Course content – A practical introduction to the
transistor-level design of memory circuits. Memory technologies including DRAM,
Flash, MRAM, Glass-based, and SRAM will be discussed.
Prerequisite EE
421 or ECG 621
Grading
25% Midterm
25% Homework/Quizzes
25%
Course Project
25% Final
Policies
·
No laptops, Internet appliances (e.g.
Kindle, Nook, Ipad, etc.), smart phones, can be used during
lectures or exams.
·
If an exam or quiz is open book then only the course textbook
can be used (no ebooks, Kindle, Nook, etc.,
older/international editions, or photocopies).
·
No late work accepted. All assigned work is due at the
beginning of class.
·
The final exam will not be returned at the end of the
semester, not even temporarily for you to review.
·
Regularly being tardy for lectures, leaving in the middle of
lectures, or earlier from lectures is unacceptable without prior consent of the
instructor.
·
Cheating or plagiarism will result in an automatic F grade in
the course (so do your own homework and projects!)
·
Email questions should be sent to the CMOSedu
Google group (not directly to the instructor) at CMOSedu@googlegroups.com.
·
Questions for the instructor (only) should be asked in person
(not via email).
After
completing ECG 721 students will be able to:
1.
Discuss the difference between an open and closed DRAM array
architecture
2.
Design, for a DRAM, an n- and p-sense amplifier, row and
column decoders, a data read/write path
3.
Design a sigma-delta sensing circuit for a Flash memory
4.
Design and simulate the operation of a charge pump for use in
generating a voltage in a memory chip
5.
Design and/or analyze an input buffer for a very-high speed
data path
6.
Design delay- and phase-locked loops for synchronization in
high-speed memory chips
7. Discuss the concerns when designing high-speed DRAM memory
chips including, the architecture limitations and how they relate to bandwidth,
latency, and cycle time, data control, and power delivery