Lab 1 - ECE 421L 

Authored by Isaac Robinson,

robins82@unlv.nevada.edu

September 7th, 2016

  

This lab focuses on completing "Tutorial 1 - Layout and simulation of a resistive voltage divider" from the Cadence Design System Tutorials on CMOSedu.com.

PRELAB:

The following image is an example of an snippit.

 snip1.JPG

The following is an example of a table generated using KompoZer.

Thequickbrownfox
jumpsoverthelazy
dog.8338

Note: return links are at the bottom of this page.

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LAB REPORT:

Following the Cadence Tutorial 1 on CMOSedu.com up to image 25 the following ciruit layout is created:

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This circuit is a simple voltage divider that has a 1 DC Volt input and two identical resistors of 1k ohm resistance.

The simulation of this circuit is ran for 1 second, and the voltage values are read at wires labeled "in" and "out".
The setup for this is seen in the image below:
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And the following is the actual simulation results:

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As can be seen in the image, the simple voltage divider drops the voltage to half the input voltage. This is expected when resistors in a simple two series resistor voltage divider have the same value in resistance.

BACKING UP:

To perform regular backups, dropbox will be used. 

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It will also hold the most recent working copy of my labs to allow them to be modified on any computer capiable of using dropbox (client or website).

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