Lab 4 - EE 421L 

Authored by Martin Jaime,

email: jaimem5 at the UNLV students domain

Date September 28th, 2016


Pre-lab work:

Snapshots from prelab:

NMOS
PMOS
media/02-sim_NMOS_schematic.jpg
media/02-sim_PMOS_schematic.jpg
media/03-sim_NMOS.jpg
media/03-sim_PMOS.jpg
media/03-sim_NMOS-extracted.jpg
media/03-sim_PMOS-extracted.jpg
media/04-sim_NMOS_layout.jpg media/0r-sim_NMOS_extracted.jpg
media/04-sim_PMOS-layout.jpg media/04-sim_PMOS_extracted.jpg

 

 
Lab Report
 

media/04-lab-sim_NMOS_ID_VDS-schem.jpg
media/06-lab-sim_NMOS_ID_VDS-sim.jpg
 
media/07-lab-sim_NMOS_ID_VGS-schem.jpg media/08-lab-sim_NMOS_ID_VGS-sim.jpg
   
media/11-lab-sim_PMOS_ID_VSD-schem.jpg
media/13-lab-sim_PMOS_ID_VSD-sim.jpg
   
media/16-lab-sim_PMOS_IV_VSG-schematic.jpg media/14-lab-sim_PMOS_IV_VSG-sim.jpg


  • Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads. 
    • Show your layout passes DRCs. 
    • Make a corresponding schematic so you can LVS your layout.
  • Lay out a 12u/0.6u PMOS device and connect all 4 MOSFET terminals to probe pads. 
    • Show your layout passes DRCs. 
    • Make a corresponding schematic so you can LVS your layout

media/17-PAD_NMOS_schem.jpg
media/19-PAD_PMOS_schem.jpg
media/18-PAD_NMOS_layout-1.jpg
media/19-PAD_PMOS_layout1.jpg
media/18-PAD_NMOS_layout-2.jpg
media/19-PAD_PMOS_layout2.jpg
media/18-PAD_NMOS_layout-DRCjpg.jpg
media/19-PAD_PMOS_DRC.jpg
media/18-PAD_NMOS_layout-LVS.jpg
media/19-PAD_PMOS_LVS.jpg



All backed up work can be found at https://github.com/martinjaime/CMOSedu-Reports


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