Lab 2

Lab 2 - EE 421L

Authored by Martin Jaime

email: jaimem5 at the UNLV students domain

September 7, 2106

Pre-lab work:

All work is being backed up to github.com

After logging in to the server, go into the ~/Downloads directory (create it if it does not exist) and run the following to download the lab2.zip, unzip it, and move it to the CMOSedu directory.

    wget http://cmosedu.com/jbaker/labs/ee421L/lab2/lab2.zip
    unzip lab2.zip
    mv lab2 ../CMOSedu

Append "DEFINE lab2 $HOME/CMOSedu/lab2" to cds.lib file to define the new lab2 directory as a new library. After moving into the CMOSedu directory, start cadence with virtuoso &. Select lab2 library, and open the schematic view of the cell sim_Ideal_ADC_DAC.

media/fig01.jpg

Run the simulation by launching ADE L. ADE will open. Load the saved state by clicking on Session > Load State and select Cellview. Click OK. Once you can see that the configuration has been properly loaded, click the green button to begin simulation.

media/fig02.jpg

Notice that the blue input signal Vin is a smooth analog signal that is converted into a 10 bit digital signal that is converted back again to an analog signal at Vout.

If we plot the digital signals, we can find out which is the LSB and the MSB. Plot for just one period of the input signal, and plot the expected LSB and MSB (B0 and B9).

media/fig04.jpg

Notice that B0 is frequently changing as is expected of the LSB. B9, the MSB, changes once in the entire 500 ns period.

Back up work
From the root of the directory containing report files commit all changes, then run git push. Backed up files can be seen at github.com/martinjaime/CMOSedu-Reports.

Lab Report

The design of a 10-bit DAC using an n-well R of 10k

The 10-bit DAC is made up of individial 1-bit DAC's as shown in Figure 6.
It is implemented with an R = 10k. The 2R portion of the voltage divider consists of two 10k resistors in series.

Figure 6

The recistance of a DAC implemented with the design used in this lab, can be performed by grounding the input terminals, and finding the equivalent resistance of that circuit. See Figure 7.

Figure 7: By recursively transforming each parallel combination of resistors into their equivalent resistance, we can see that we ultimately obtain an output resistance of R, despite how large the DAC may be. Each parallel combination results in the sum of the series yielding another pair of of parallel 2R resistors.

Delay, driving a load

With all the DAC inputs grounded except for B9, the DAC drives a drives a 10 pF load. The input voltage is a pulse source (0 to VDD) into B9.
Knowing that the 50% time delay td is 0.7RC, then td = 0.7 * 10k * 10p = 70 ns.
Figure 8 illustrates the simulation results that match the calculations with its respective schematic.

Figure 8

How to create a symbol view for your design with the exact same footprint as the Ideal_10-bit_DAC symbol view (hint: use Copy before you start drafting your design, e.g. Copy the cell Ideal_10-bit_DAC to Mydesign_10-bit_DAC and then simply edit the schematic view!)

See Tutorial 1 for additional help
Note that your design won't use VDD, Verfp, or Vrefm so you can delete those pins on your design's DAC symbol view

How to create a symbol view for the DAC design with the same exact footprint as the Ideal_10-bit_DAC symbol view.

In the schematic view, go to through the menus Create > Cellview > From Cellview. With the settings as seen in Figure 9, click "OK". In the next window that pops up, arrange the setting of the pins to your liking, and click "OK".
Then the symbol editor will appear where you can edit the appearance of the symbol.

Figure 9

Simulations to verify the design functions correctly.

Ideal	My Design


As we can see in these simulation results, the DAC made up of R resistors works similarly with little precision lost. The new design works as expecte.

There were convergence problems while trying to simulate the circuit with the new DAC. The simulation was forced to converge by going to, in the ADE, Simulation -> Options -> Analog

Set the values as seen below

relative tolerance, reltol, of 10% (= 1e-1)

voltage absolute tolerance, vabstol, of 100 mV (= 1e-1)

current absolute tolerance, iabstol, of 1 mA (= 1e-3)

However, if the design drives a load, we get different results. In the following figures, the ADC to DAC design is tested driving a load R = 10k, C = 10p, and both R and C.

	Notice that since we now have a resistive load that is equal to the resistance of the DAC, the amplitude drops by half.
	With an RC load, the amplitude drops, with a phase shift. The output signal is also smoothed by the capasitive load.
	Without the resistor, the output has the same phase shift, with a smaller voltage drop.

In a real circuit the switches seen above (the outputs of the ADC) are implemented with transistors (MOSFETs).

When the circuit is implemented as a measuerement device, or for monitoring a signal to communicate, it must be as unintrusive as possible. With a very high input resistance, the effects of the load are less significant.

All backed up work can be found at https://github.com/martinjaime/CMOSedu-Reports

EE421L Lab Student Listing | My Lab Directory | EE421L Home Page