Authored by Jonathan Young on November 2, 2015
Email: youngj1ATunlv.nevada.edu
Lab Description:
This lab demonstrates how to create a schematic, symbol, simulation schematic, and simulations for common gates (AND, OR, NAND, NOR, and Inverter) in their standard configuration and in an 8-bit configuration. This is accomplished by using buses and arrays in their respective designs. This lab also includes the design of a mux/demux in 2-bit and 8-bit configurations, as well as a full adder in both 1-bit and 8-bit configurations, including the layout of the 8-bit configuration.
Pre-Lab:
1. Back-up all of your work from the lab and the course.
2. Go through Tutorial 5 seen here.
3. Read through the entire lab before starting it.
Ring Oscillator:
Figure 1:
This image shows the schematic layout of a 31-ring oscillator by connecting inverters together in a chain, with the ends connecting back on each other. Note: VDD is used as a stimuli.
Figure 2:
This image shows a close-up of the 31-ring oscillator in figure 1, where the output of the last gate is looping back to the first inverter in the chain. Note: It is called osc_out.
Figure 3:
This image shows the simulation of the 31-ring oscillator showing that it oscillates on and off continuously.
Figure 4:
This image shows a 31-ring oscillator using a cleaner schematic. Instead of using 31 inverters connected together, as was done in Figure 1, the inverter here was instantiated 31 times. This allows us to use a bus and array configuration to achieve the same 31-ring oscillator from figure 1. Note: VDD is used as a stimuli.
Figure 5:
This image shows the layout of two inverters next to each other, for preparation of the 31-ring oscillator layout. Note: DRC returned no errors and thus this design is valid, until checked with LVS to see if it is functionally identical to the schematic.
Figure 6:
This image shows the same layout of figure 5, but with a display level of 0 to allow one to see the metal1 connections.
Figure 7:
This image shows the layout of a single inverter, being copied 30 times to allow us to create a 31-ring oscillator layout with minimal effort.
Figure 8:
This image shows the whole 31-ring oscillator layout. Note: There are 31 inverters present in this layout.
Figure 9:
This image is the same as figure 8, with the display level set to 0 to show both the metal1 and metal2 connections across the inverters.
Figure 10:
This image shows the close-up of figure 9, showing the right most side with the connections to vdd!, gnd!, and osc_out as shown previously in figure 2.
Figure 11:
This image shows the resulting schematic of the 31-ring oscillator, with vdd present.
Figure 12:
This image shows that the 31-ring oscillator layout passed DRC without any errors.
Figure 13:
This image shows the extracted 31-ring oscillator layout and that it passed LVS without issues as the netlists match.
Figure 14:
This image is of the 31-ring oscillator symbol, to realize the schematic in figure 11.
Figure 15:
This image shows the simulation schematic, which is used to produce simulations as seen in figure 16.
Figure 16:
This image shows the simulation of the schematic in figure 15.
Figure 17:
This image shows the extracted layout simulation of the schematic in figure 15.
Post-Lab:
1. For your lab report please use cell names that indicate the current semester and your initials.
2. Show, in your lab report, how a capacitive load influences the delay and rise/fall times. For the creation of a 4-bit inverter.
3. Create schematics and symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR gates.
4. Provide a few simulation examples using these gates.
5. Simulate the operation of this circuit (mux/demux) using Spectre and explain how it works.
6. Make sure to show, using simulations, how the circuit (mux/demux) can be used for both multiplexing and de-multiplexing.
7. Create an 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol. Include an inverter in your design so the cell only needs one select input, S (the complement, Si, is generated using an inverter).
8. Use simulations to verify the operation of your design.
9. Draft the schematic of the full-adder seen in Fig. 12.20 using 6u/0.6u devices (both PMOS and NMOS).
10. Create an adder symbol for this circuit (see the symbol used in lab6).
11. Use this symbol to draft an 8-bit adder schematic and symbol.
12. For how to label the bus so the carry out of one full-adder goes to the carry in of another full-adder review the ring oscillator schematic discussed in Cadence Tutorial 5.
13. Simulate the operation of your 8-bit adder.
14. Lay out this 8-bit adder cell (*note* that this is the only layout required in this lab).
15. Show that your layout DRCs and LVSs correctly.
16. The cells provided in the lab write up instructions, can be downloaded by clicking here.
17. Backup your work.
Inverter Gate:
The following images use the inverter schematic laid out in Tutorial 3, as seen in the pre-lab for lab 5, figure 1. This schematic can be found by clicking here.
Figure 18:
This image shows the schematic of a 4-bit inverter which was created with arrays and buses. Note: The symbol is that of the inverter schematic, as discussed above.
Figure 19:
This image is the symbol for the schematic in figure 18, which will be used in the simulation schematic to ensure that the 4-bit inverter works as intended.
Figure 20:
This is the schematic which will be used for testing the 4-bit inverted. There are four different load types connected to the inverter. The first <3> carries a 100fF load, the second <2> carries a500fF load, the third <1> carries a 1pF load, and the fourth <0> carries no load.
The following image, simulation, shows the output of each load corresponding to the four individual wires of the bus. The capacitive loads influence the rise and fall times of the inverter's output by slowing down the time it takes for the output to rise and fall. Instead of having the inverter's output rise and fall times flow in an abrupt straight manner, the output is slowed to gentle slopes. The smaller the load, the more it resembles a no capacitive load with faster rise and fall times, i.e. the 100fF load on <3>. The larger the capacitance the longer it takes the output to rise and fall for the output to reach their plateau flat line (either on or off solid). The <2> output has a 500fF load and thus slows down more so than the <3> output. The <1> output has biggest capacitive load of 1pF and thus has slower rise and fall time out of all the other outputs. In digital design, this is not preferred as it could cause invalid signals to appear in the circuit. If the application requires such a slow signal then this is how it is achieved. Both design considerations are dependent on the circuit being designed.
Figure 21:
This image shows the simulation with the capacitive loads, i.e. of the schematic in figure 20.
Figure 22:
This image shows the schematic of an 8-bit inverter.
Figure 23:
This image shows the symbol of the previous figure, for an 8-bit inverter.
Figure 24:
This image shows the simulation schematic of an 8-bit inverter.
Figure 25:
This image shows the simulation results of the schematic in the previous figure. Note: All the outputs are the same, thus showing successful operation.
NOR Gate:
Figure 26:
This image shows the schematic of a 2-bit NOR gate.
Figure 27:
This image shows the standard gate symbol for the NOR gate, which references the schematic in the previous figure.
Figure 28:
This image shows the schematic of an 8-bit NOR gate, using the symbol in the previous figure for instantiation.
Figure 29:
This image shows the standard gate symbol for an 8-bit NOR gate, with a x8 shown inside.
Figure 30:
This image shows the simulation schematic of an 8-bit NOR gate.
Figure 31:
This image shows the successful simulation of the 8-bit NOR gate schematic seen in the previous figure. Note: This simulation tests the following conditions: 00, 01, 10, and 11.
NAND Gate:
Figure 32:
This image shows the schematic of a 2-bit NAND gate.
Figure 33:
This image shows the standard gate symbol for the NAND gate, which references the schematic in the previous figure.
Figure 34:
This image shows the schematic of an 8-bit NAND gate, using the symbol in the previous figure for instantiation.
Figure 35:
This image shows the standard gate symbol for an 8-bit NAND gate.
Figure 36:
This image shows the simulation schematic of an 8-bit NAND gate.
Figure 37:
This image shows the successful simulation of the 8-bit NAND gate schematic seen in the previous figure. Note: This simulation tests the following conditions: 00, 01, 10, and 11.
AND Gate:
Figure 38:
This image shows the schematic of a 2-bit AND gate.
Figure 39:
This image shows the standard gate symbol for the AND gate, which references the schematic in the previous figure.
Figure 40:
This image shows the schematic of an 8-bit AND gate, using the symbol in the previous figure for instantiation.
Figure 41:
This image shows the standard gate symbol for an 8-bit AND gate.
Figure 42:
This image shows the simulation schematic of an 8-bit AND gate.
Figure 43:
This image shows the successful simulation of the 8-bit AND gate schematic seen in the previous figure. Note: This simulation tests the following conditions: 00, 01, 10, and 11.
OR Gate:
Figure 44:
This image shows the schematic of a 2-bit OR gate.
Figure 45:
This image shows the standard gate symbol for the OR gate, which references the schematic in the previous figure.
Figure 46:
This image shows the schematic of an 8-bit OR gate, using the symbol in the previous figure for instantiation.
Figure 47:
This image shows the standard gate symbol for an 8-bit OR gate.
Figure 48:
This image shows the simulation schematic of an 8-bit OR gate.
Figure 49:
This image shows the successful simulation of the 8-bit OR gate schematic seen in the previous figure. Note: This simulation tests the following conditions: 00, 01, 10, and 11.
Multiplexor (MUX):
A 2-to-1 MUJX circuit works by activating (putting it high) the selection input, S, allows the output, Z, replicate the signal coming in from the input line A. If S is low, then Z will replicate the B input line. When replicating these lines, they will be exactly the same and thus any changes that occur on the input lines will be reflected on the output line depending upon which state S is in (high or low). This design is accomplished using MOSFETs, with the selection line S being inverted and allowing the PMOS holding back A to pass through to the output. Conversely, the NMOS connected to B is given the opposite of S, a low signal, and the PMOS of B is given a high input. This prevents the signal of B from passing through unless the S is low. When S is low, the inputs to B's NMOS and PMOS are switched thus allowing B to pass through. This detail is evident in the images seen below.
Figure 50:
This image is the schematic of a 2-to-1 MUX realized with MOSFETs.
Figure 51:
This image is the symbol of a 2-to-1 MUX, created from the schematic in the previous image.
Figure 52:
This image is the simulation schematic of the 2-to-1 MUX.
Figure 53:
This image shows the simulation results produced from the schematic in the previous figure.
Figure 54:
This image shows the schematic of an 8-bit 2-to-1 MUX, using the symbol created in Figure 51.
Figure 55:
This image is the symbol of an 8-bit 2-to-1 MUX.
Figure 56:
This image shows the simulation schematic of an 8-bit 2-to-1 MUX.
Figure 57:
This image shows the simulation results produced from the previous figure. As one can see, when S is low the output, Z, is whatever B is. When S is high, the output, Z, is whatever A is as discussed at the beginning of this section.
De-Multiplexor (DEMUX):
The DEMUX is the reversed of the MUX. Instead of selecting from multiple input lines to pass through to the single output, Z, line; the DEMUX works by setting the input lines of the MUX as output lines and the output line of the MUX as an input line.
Figure 58:
This image is the schematic of a 2-to-1 DEMUX realized with MOSFETs.
Figure 59:
This image is the symbol of a 2-to-1 DEMUX, created from the schematic in the previous image.
Figure 60:
This image is the simulation schematic of the 2-to-1 DEMUX.
Figure 61:
This image shows the simulation results produced from the schematic in the previous figure.
Figure 62:
This image shows the schematic of an 8-bit 2-to-1 DEMUX, using the symbol created in Figure 51.
Figure 63:
This image is the symbol of an 8-bit 2-to-1 DEMUX.
Figure 64:
This image shows the simulation schematic of an 8-bit 2-to-1 DEMUX.
Figure 65:
This image shows the simulation results produced from the previous figure. As one can see, the output stream A follows the input pattern, Z, when S is high and the output stream B when S is low.
Full Adder:
This section covers the design a full adder and its conversion into an 8-bit full adder, including the layout. For additional information on the full adder, including how it works, reference the full-adder section from lab 6 by clicking here.
Figure 66:
This image shows the schematic of the full adder with carry-in using MOSFETS only, as seen in figure 12.20 in the CMOS 3rd Edition Book by Dr. Baker.
Figure 67:
This image is the symbol of the full adder generated from the schematic in the previous figure.
Figure 68:
This image is of the simulation schematic to verify functionality of the full adder.
Figure 69:
This image is the simulation results produced from the schematic in the previous figure. Note: How when A and B are 0, with Cin being 1 that S(Sum) is 1 and that Cout (Carry Out) is 0. As the simulation continues, the circuit continues to respond correctly to the change of inputs and produces the correct output.
Figure 70:
This image is of the schematic for an 8-bit full adder, using the symbol generated in figure 67.
Figure 71:
This image is of the symbol of an 8-bit full adder generated from the previous figure.
Figure 72:
This image is of the simulation schematic to verify functionality of the 8-bit full adder.
Figure 73:
This image is the simulation results produced from the schematic in the previous figure. The sum of 01101010 and 10110101 is 100011111. Along with the Cin, the total is 100100000. Our output has only has Cout high, and out<5> high, indicating a correct output.
Figure 74:
This image shows the layout of the 8-bit full adder and that it has no DRC errors.
Figure 75:
This image shows a closeup of the layout of the 8-bit full adder.
Figure 76:
This image shows the extracted layout of the 8-bit full adder and that it has no LVS errors.
Figure 77:
This image shows a close up of the extracted layout of the 8-bit full adder.
Back Up
The lab directory containing the layouts, schematics, simulations, and symbols generated in this lab report can be downloaded by clicking this link: lab7_JMY.zip. This link is provided for informational and grading purposes only. All other use is prohibited.
