EE 421L Digital Electronics Lab #6

Authored by Jonathan Young on October 19, 2015
Email: youngj1ATunlv.nevada.edu

Lab Description:

This lab demonstrates how to layout a two-bit NAND gate, two-bit XOR gate, and a Full Adder. After the layouts are generated, their extracted layout simulations are compared to their schematic simulations to verify operations. Note: This lab uses the inverter created for Lab #5.

Pre-Lab:

1. Back-up all of your work from the lab and the course.
2. Go through Cadence Tutorial 4 seen here.
3. Read through the lab in its entirety before starting to work on it.

NAND Gate:

The following will show the layout, schematic, and symbol of the NAND gate created by following Tutorial 4.

Figure 1: This is a schematic of a two-input NAND gate, which is created using two-inverters from Lab 5. These inverters (MOSFETS) are 6u by 0.6u.
Figure 2: This is a symbol of a two-bit NAND gate, which is of form (logic symbol).
Figure 3: This image is the schematic used for simulation purposes of the two-input NAND gate.
Figure 4: This image is the simulation of the two-input NAND gate seen in figure 3.
Figure 5: This image is the layout of the two-input NAND gate.
Figure 6: This image shows the layout of the two-input NAND gate, verifying that it had no Design Rule Check (DRC) errors.
Figure 7: This image is of the extracted layout, showing no Layout VS. Schematic (LVS) errors as the netlists of the schematic in figure 1 and of the layout in figure 5 match.
Figure 7_1: This is a close-up image of the extracted layout seen in Figure 7, above.

Post-Lab:

1. Draft the schematics of a 2-input NAND gate (Fig. 12.1), and a 2-input XOR gate (Fig. 12.18) using 6u/0.6u MOSFETs (both NMOS and PMOS).
2. Create layout and symbol views for these gates showing that the cells DRC and LVS without errors.
3. Ensure that your symbol views are the commonly used symbols (not boxes!) for these gates with your initials in the middle of the symbol.
4. Ensure all layouts in this lab use standard cell frames that snap together end-to-end for routing vdd! and gnd!
5. Use a standard cell height taller than you need for these gates so that it can be used for layouts that are more complicated in the future.
6. Ensure gate inputs, outputs, vdd!, and gnd! are all routed on metal1.
7. Use cell names that include your initials and the current year/semester, e.g. NAND_jb_f19 (if it were fall 2019)
8. Using Spectre simulate the logical operation of the gates for all 4 possible inputs (00, 01, 10, and 11).
9. Comment on how timing of the input pulses can cause glitches in the output of a gate
10. Your html lab report should detail each of these efforts.
11. Using these gates, draft the schematic of the full adder. Create a symbol for this full adder; simulate using Spectre, the operation of the full adder using this symbol.
12. Layout the full adder by placing the 5 gates end-to-end so that vdd! and gnd! are routed full adder inputs and outputs can be on metal2 but not metal3. Do an LVS and DRC for this full adder design. Note: These cells provided in the lab write up instructions, can be downloaded by clicking here.

NAND Gate:

Figure 8: This image is an updated symbol of the NAND gate shown in the pre-lab, with the addition of my initials. All of the layouts received minor adjustments but are relatively the same as the pre-lab and thus should be consulted when referencing the full adder later in this lab report.

XOR Gate:

Figure 9: This image is the schematic layout of an XOR gate. Note: It makes heavy use of the inverters from Lab #5.
Figure 10: This image is of the standard XOR logic gate symbol, which includes my initials.
Figure 11: This image is the layout of the schematic from figure 9. It also shows no DRC errors in this design.
Figure 12: This is the extracted layout from figure 11. Note: This is a close up.
Figure 13: This image shows the extracted layout of the XOR gate, including the fact that it LVSed without issues and ensuring that the netlists match.

Gate Simulations:

Figure 14: This schematic is for simulation purposes, to show the NAND, XOR, and inverter operations.
Figure 15: This image shows the voltage source setup, used for simulations of the gates in figure 14.
Figure 16: This image shows the simulation setup of figure 14.
Figure 17: This image shows the simulation of the schematic of figure 14.
Figure 18: This image shows the extracted layout simulation of each gate. Note: This simulation and the one in figure 17 both show the simulations of each gate with the fulling inputs 00, 01, 10, and 11.

Both the extracted simulation and schematic only simulation have produced the desired output results based on the inputs. Since the NAND gate is the inverse of the AND gate, all input combinations produce an output high (1) unless both inputs are high in which case the output will be low (0). For the XOR gate, if the inputs match, i.e. if they are either 00 or 11, then the output will be low (0). Otherwise, if they are different, then they are exclusively one or the other and thus an output of high (1) is seen. The timing of the gate signals being appropriately timed is a critical factor in the output of the gate. If a gate input pulse is not appropriately timed, this can cause an erroneous signal to output by feeding the wrong information to the input of the gate.

Full Adder:

Figure 19: This image is the schematic of the full adder, using the previously created gates.
Figure 20: This image is the symbol used for the full adder, including my initials. Note: This is the standard logic symbol for a full adder.
Figure 21: This image is of the full adder, using the symbol, for simulations.
Figure 22: This image is of the simulation, using the schematic seen in figure 21.
Figure 23: This image is the close-up layout of the full adder circuit.
Figure 24: This image is of the full adder layout, showing no DRC errors.
Figure 25: This image is of the extracted layout of the full adder.
Figure 26: This image shows that the extracted layout matches the schematic, and thus no LVS errors.
Figure 27: This image shows the extracted layout simulation of the full adder circuit, similar to that seen in figure 22.

For reference, a truth table for the full adder is seen below. This is useful for verifying the above simulations to ensure it operates as it was designed to and produce the values from the truth table.

Back Up:

The lab directory containing the layouts, schematics, and symbols generates in this lab report can be downloaded by clicking this link: lab6_JMY_F15.zip. This link is provided for informational and grading purposes only. All other use is prohibited.

Note: The cell names used in this lab were changed after simulations and layout to match those requested in the post-lab, #7, and thus may differ slightly when loading the zip.