Jonathan Young's EE 421 Digital Electronics Lab

Tutorial 3:

Schemtic of 12u/6u Inverter — **Figure 1:** The image above, shows an inverter created with a PMOS (w=12.0um and l=600nm) and an NMOS (w=6um and l=600nm). Note: The A pin is the input into the inverter, which drives both MOSFET's gates. The Ai pin is the output pin which comes directly from the drain of boh MOSFETs. Also of interest is that the body of the NMOS is connected directly to ground and the PMOS body is connected directly to VDD.

Symbol of Schematic in previous figure — **Figure 2:** This image shows the symbol created based off the schematic in Figure 1.

Schematic using Symbol from previous figure — **Figure 3:** This image shows the schematic using the symbol created in Figure 2 to drive an input with a voltage source and an output pin. This schematic will be used for simulation purposes.

Simulation of Figure 3 Schematic — **Figure 4:** This image shows the simulation results of Figure 3's schematic. Note: As the input rises in voltage that the output remains at zero, thus the input is inverted. This is the desired result of an inverter circuit.

**Figure 5:** This image is a schematic of the inverter shown previously in Figure 3, but with the addition of VDD (it does not need to be connected to the circuit, doing so will result in a faulty schematic and simulation), which is shown in the schematic in Figure 1.

**Figure 6:** This image shows the simulation results of Figure 5. Note: VDD is 5V and thus as the input voltage increases on the gates it is inverted thus showing the actual operation of the inverter.

**Figure 7:** This image shows the extracted simulation, unlike that of the previous figure. Note: The results are identical.

Post-Lab:

1. Draft schematics, layouts, and symbols for two inverters having sizes of: 12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u) and 48u/24u where the devices use a multiplier, M = 4.
2. Your schematics should have two pins, e.g., A and Ai.
3. Your layouts should have 4 pins: A, Ai, vdd!, and gnd! (note how lowercase letters are used for power and ground).
4. Your lab reports should document your efforts and results including showing that the extracted layouts and schematics LVS correctly.
5. Zip up these cells in a directory call lab5_rjb.zip (last two or three letters are your initials) and link to your lab report.
6. Using SPICE simulate the operation of both of your inverters showing each driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load. Comment, in your report, on the results.
7. Use UltraSim (Cadence's fast SPICE simulator for larger circuits at the cost of accuracy) and repeat the above simulations.Note that UltraSim only performs transient simulations (not AC, Noise, DC, operating point, etc.). Not knowing this will lead to wasted time if trying to use UltraSim exclusively for simulations.
8. The cells used to generate the images used on the lab instruction webpage are found in lab5.zip.

Layout of 12um/6um Inverter:

**Figure 8:** This image shows the layout of an inverter with a PMOS width of 12um and an NMOS width of 6um. The length of both MOSFETs is 600n.

**Figure 9:** This image is the corresponding schematic of the layout seen in Figure 8.

**Figure 10:** This image shows the layout, identical to Figure 8, but showing that the layout DRCed without errors.

**Figure 11:** This image is the extracted layout, showing the position of both the PMOS and NMOS circuits. It also shows that the layout LVSed without errors (netlists match), when comparing the extracted layout to the schematic of Figure 9.

**Figure 12:** This image is the symbol generated from the schematic in Figure 9. Note: The look of this symbol was created manually with a note indicting it is a 12u/6u inverter, with the 12u corresponding to the width of the PMOS and the 6u corresponding to the width of the NMOS.

Layout of 48um/24um Inverter:

**Figure 13:** This image shows the symbol generated similar to the previous figure, but with the note changed from 12u/6u to 48u/24u. This implies that the width of the PMOS is 48u and that the width of the NMOS is 24u.

**Figure 14:** This image shows the schematic of the 48u/24u inverter layout. Note: Unlike Figure 9, the m value has changed from 1 to 4 thus multiplying the size of the PMOS and NMOS devices.

**Figure 15:** This image is the layout of the 48u/24u schematic seen in the previous figure. As the multiplier increased, the number of columns were obviously increased. The remaining part of the circuit had to be stretched with more metal1 and Poly1 being added to connect the rest of the circuit. This layout also returned no DRC errors.

**Figure 16:** This image shows the extracted layout from Figure 15. It clearly shows that there are indeed 4 PMOS circuits and 4 NMOS circuits, which is what increasing the value of M did. This layout also LVSed without errors when comparing the extracted layout to Figure 14.

SPICE Simulation:

The following images show the inverter driving capacitive loads from 100ff, 1pf, 10pf, and 100pf. A note about capacitors, the larger the value of the capacitor, the longer it takes for it to build up charge (voltage). This also applies to discharging. Thus, if a capacitor has a small value then it will quickly charge and discharge. The simulations were conducted using the following schematic:

**Figure 17:** This image shows the simulation schematic of the inverter driving capacitive loads. Note: The 12u/6u will be switched to 48u/24u when simulating those circuits with no other changes made to the schematic. This schematic will also be used for the UltraSim simulations below.

**Figure 18:** This simulation is of the 12u/6u inverter driving a 1pF load. Notice how the load shows the inverter working with small delay in the fall and rise times, but once these times are factored in the inverter does indeed invert the input.

**Figure 19:** This simulation is of the 12u/6u inverter driving a 10pF load. Notice how the output starts to invert but is stopped before the end of the pulse, this is because the capacitor is supplying the charge (draining) and thus preventing the output from being fully inverted. If this simulation is continued, the output will essentially be a saw-tooth wave.

**Figure 20:** This simulation is of the 12u/6u inverter driving a 100fF load. Notice how the smaller the capacitors is the closer the output is to the desired value of the inverter.

**Figure 21:** This simulation is of the 12u/6u inverter driving a 100pF load. Notice that with a high value capacitor as a load that the output dips slightly when the input is inverted, but the output is still essentially the input (i.e. a simi-straight line).

The information about capacitors is the same, as discussed previously in this section. Due to the transistors having an increased width, more current can flow, and thus more electrons are free to pass through. With these increased passage ways, the capacitive load should charge and discharge quicker and produce the RC charge/discharge curve we're accustomed to seeing as opposed to saw tooth patterns.

**Figure 22:** This simulation is of the 48u/24u inverter driving a 1pF load. Notice that this circuit's output charges and discharges more quickly than that of the 12u/6u inverter.

**Figure 23:** This simulation is of the 48u/24u inverter driving a 10pF load. Notice how the 12u/6u produced a saw tooth wave and how this one fully charges and discharges.

**Figure 24:** This simulation is of the 48u/24u inverter driving a 100fF load. Notice the results are near identical for the 12u/6u inverter.

**Figure 25:** This simulation is of the 48u/24u inverter driving a 100pF load. Notice that this produces a saw tooth wave, unlike that of the 12u/6u inverter.

UltraSim Simulation:

This simulator allows for fast simulation results, but at the cost of inaccuracies. Thus, the output is not expected to be as precious as the previous simulations.

EE 421L Digital Electronics Lab #5

Lab Description:

Pre-Lab: