Authored by Jonathan Young on September 21, 2015
Email: youngj1ATunlv.nevada.edu
Lab Description:
This lab, in conjunction with Lab 2, went through the creation of a 10-bit Digital to Analog converter (DAC). While Lab
2 focused on the schematic layout using the R-2R topology; Lab 3 focused on taking that schematic layout and turning it
into a layout using the 10k n-well resistors.
Pre-Lab:
1. Back up all of your previous work from the lab and the course. 2. Finish Tutorial 1.
Back-Up:
Figure 1:
This image shows a sub-folder back up of all my course work so far in this course including cadence. As we progress
through the lab and course, back ups are maintained by copying the files from my Windows Virtual Machine over to my
Macintosh which is then also backed up by Time Machine, thus insuring I have copies of any and all changes made since my
submission of my course work.
Tutorial 1:
Continuing where we left off in Lab 1, after the simulation of the schematic and creation of the symbol for a voltage
divider, a layout using the n-well will be created. This process will be explained below, though not in minute detail as
described in Tutorial 1, which can be found by clicking here.
To create an n-well
resistor, such as the 10k n-well resistors needed for our 10-bit DAC, a new cell view is created that is titled
"R_n_well_10k" to denote that it is resistor based on the n-well and that it is of 10k value. This layout is what is
used to physically build the 10k resistor using the CMOS process, since we are using a C5 process, the correct size
dimensions must be realized. To determine the value, read length and width of our n-well, a calculation must be
performed as well as knowing which design rules are being used.
In this course and lab, the MOSIS submicron
(SCUBM) design rules are used as this is how integrated circuit chips will be produced at the end of the semester. To
produce such chips, design rules from the manufacture must be followed. These rules specify the minimum well width,
minimum spacing between wells at different potential, minimum spacing between wells at the same potential, and minimum
spacing between wells of different types (p-well for example). These rules and sizes are displayed out in the table
below:
Note: CMOSedu is also present as the course textbook uses this scale as well, which is half that of the SUBM that MOSIS
uses. The lambda next to each number indicates a scaling factor.
Since the C5 (300nm=0.30um) process is being
used, the minimum width of an n-well using this process is calculated by the following: 12lamda*0.3um=3.6um. Using this
width, the length must now be determined. An n-well resistor is created with the following formula: r=length/width*sheet
resistance (ohm/square). Sheet resistance for this process is roughly 800 ohm/sheet. Thus, using the above formula,
including the width calculated above and the known resistor value needed (10k), the following will determine the length
of the n-well needed: Length=Resistor/Sheet Resistance * width=10k/800 * 3.6um=46um.
Thus, to create a 10k
resistor using an n-well with the C5 process, the length must be 46um and the width must be 3.6um. However, Tutorial 1
is using a 4.5um width (56.25um length - this is valid, since this is greater than the 3.6 minimum this process allows)
which I will be using to layout my n-well as described below. The reason for this variance is to give a little extra
error as the MOSIS process is not 100% perfect, thus if the minimum value was used the chip may not fabricate correctly
as it could end up with a 4.0 minimum length. Thus it is best to design a little over the exact minimum values.
Figure 2:
This image shows the blank layout in Cadence, when first starting up the cell view. This is where
the n-well will be created and how the IC will be fabricated.
Figure 3:
This image shows the n-well layout of the resistor. This is a rectangular box, using the n-well layout with the sizes
being displayed in the image above. Note: That these sizes match the hand-calculations done above.
Figure 4:
This image shows the NTAP being added to both ends of the resistor. These NTAPs are created with two contacts on each
side to allow connection to the pins of the resistor in the n-well level.
Figure 5:
This image shows the resistor id (res_id) which tells Cadence that this n-well is a resistor. I.e. it identifies what
component we are building in the IC.
Figure 6:
This image shows the actual value obtained with the hand-calculations and layout from the previous figures. Note: The
resistance is a little off and this is valid as in the real world nothing is a 100% perfect process. Thus this
resistance may go up or down based on the actual manufacture's process of the IC as well as the quality of the wafer
used.
This image also shows how a circuit can be measured to verify that the length and width of the n-well resistor was done
correctly. Using the Ruler Tool in Cadence, allows portions of the nwell to be measured thus aiding in the verification
of the length and width of the n-well resistor to match the hand-calculations.
Figure 7:
This figure shows the testing of the 10k n-well (extracted layout) created in the previous figures to determine if it
functions correctly as intended. Note: The extracted layout allows us to simulate using the full value of the resistor
created and not those built into SPECTRE (SPICE simulation). In addition, since this is in a voltage divider circuit,
the output is expected to be half of the input wave, which is seen above. Comparing this to the figure from Lab 1, we
see minor differences in voltage but these still achieve the desired affect and is in the acceptable range.
Post-Lab:
1. Use the n-well to layout a 10k resistor as discussed in Tutorial 1.* 2. Discuss how to select the width and
length of the resistor by referencing the process information from MOSIS.* 3. Use this n-well resistor in the layout
of the 10-bit DAC. 4. Discuss how the width and length of the resistor are measured.* 5. Ensure that each
resistor in the 10-bit DAC is laid out in parallel having the same xposition but varying y-positions (the resistors are
stacked). Note: All input and output pins should be on metal 1. 6. DRC and LVS, with the extracted layout, the
10-bit DAC design. Include the final design directory as a compressed file and provide a download link. Note: *
indicates this task was performed as part of the pre-lab above.
10K n-well Layout:
This layout was done in the pre-lab, as discussed above as well as how to select the width and
length of the resistor using the process information from MOSIS. Since this information has
already been discussed previously in the report, the use of the 10k n-well will be used for the
10-bit DAC.
10-bit DAC:
To create the 10-bit DAC, the use of three 10k n-well resistors will be used. This creates the 2R to R resistor topology
seen in lab 2, figure 10.
Figure 8:
This image shows the layout of the 2R to R topology for a single bit DAC. The 2R is a connection of two 10k n-well
resistors in series, followed by the connection R, which is a single 10k n-well resistor. This is essentially a voltage
divider. The above image shows the spacing between each n-well resistor, as well as the three pin connections: Input
(In), output (Top), and ground (Bottom).
The Top and Bottom pins are bi-directional pins, to allow for easier chaining of this circuit for the remaining 9-bits
of the DAC to create the final design of a 10-bit DAC. This is just a small subset of that circuit, a single bit. The
distance shown above, 5.4um, was calculated using the MOSIS table from the pre-lab. Since the potential (voltage)
changes between the n-wells because of the voltage divider, the calculation formula is: 0.3um*18=5.4um. This is the
minimum distance that must be between the three n-wells, as displayed above.
Figure 9:
This image shows the extracted layout of the layout in the previous figure. This also shows that each resistor is of
10.21k, which is just a little more than the 10k ohm resistor value that was desired. Due to imperfections in the MOSIS
manufacturing process this is acceptable.
Figure 10:
This image shows that the layout of the 2R to R topology DRCed and LVSed without errors and matched perfectly with the
netlist of the schematic.
To create the 10-bit DAC, the above 1-bit DAC will be duplicated ten times and inter-connected. Lastly, at the
end due to the total resistance of the 2R to R topology having the resistance of R. To realize this circuit, we must add
another 10k n-well to the ten bit DAC, as explained in the previous lab (lab 2).
The following is the final 10-bit DAC design.
Figure 11:
This image is a close-up of the inter-connection between two 1-bit DACs.
Figure 12:
This image shows the extracted layout of the previous figure. This confirms the connections and the resistor values
being 10.21k ohms.
Figure 13:
This image shows the layout of the 10-bit DAC, with all 1-bit DAC components linked up including the additional 10k ohm
n-well resistor at the bottom of the image.
Figure 14:
This image is the extracted layout of the full 10-bit DAC, zoomed out to fit the whole layout. Referring to the close
up images above, one can see that these values are consistent throughout the layout.
Figure 15:
This image shows the whole 10-bit DAC encountered no DRC or LVS errors and thus was fully
functional, including that the netlists matched the schematic from Lab 2.
Figure 16:
This image shows the simulation, as seen in Figure 14 of lab 2, but with the extracted values. The image is a little
cleaner than seen previously
Figure 17:
This image is similar to that of figure 16 in lab 2, with the delay being increased slightly which is due to the minor
change in the resistor values. This changes the time constant in the RC circuit.
Figure 18:
This image is very similar to that seen in figure 18 in lab 2.
Figure 19:
This image is very similar to figure 20 from lab 2, with changes being non-discernable.
Figure 20:
This image is very similar to figure 22 of lab 2, with changes being non-discernable.
In all, the simulations above show very minor changes from the schematic simulated layout versus the extracted layout
simulations. The changes that were encountered were do to the small change in the actual resistance when no load was
attached.
The final design compressed file can be downloaded by clicking here. This file
contains the 10- bit DAC layout, simulations, as well as schematic and symbols. This file is provided for grading and
verification purposes only.
