Lab 1 - ECE 421L

See the EE421L webpage here

Authored by Juan Buendia,

buendiaj@unlv.nevada.edu

August 23, 2015

Objective - Laboratory introduction, generating/posting html lab reports, due August 31 (to see the full lab click here)

Prelab - Setup our Lab Report webpage, and publish it on the internet with a folder named "Lab 1."

The lab directed us to create an ftp folder using windows Explorer.

Using snipping tool we cut out a jpg file to save it on our ftp folder (to get used to how to create jpg images using snippingtool).

In order to edit our lab reports in the web, we will be using a program named kompozer 

Class	Assignment	Lab Number	Font	Size	Program Used
EE421L	Pre lab	1	Comic Sans MS	13.5	Kompozer

Post Lab- Layout and simulation of a resistive voltage divider

This is an introduction to Cadence 6.1 which is used for chip design, layout, and simulation.

To begin we needed to download Mobaxterm (an enhanced terminal for Windows with X11 server, tabbed SSH client,netword tools, and more) and setup our Cadence account.

After a few more modifications to our account, we are now ready to use Cadence to perform multiple simulations, schematics, and chip designs.

After this we added a new libray (I called it EE421L_Lab_1), and verified the "define" line was added to the cdslib.

We were then directed to create a voltage divider with two 10K resistors and a 1 VDC source.

We were then directed to simulate the above schematic by opening the ADEl and using Spectre as the simulator.  I expect the output to reflect the following equation:

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