Lab 4 - ECE 421L

Authored by: WENLAN WU (Stephen)

E-mail: wuw2@unlv.nevada.edu

Date: 9/25/2013

 


Lab description

1.  Go through the tutorial_2 of Electric from CMOSedu.com.  Study how to design the schematic & layout of NMOS/PMOS.

2. Backup the Lab report and upload it to the CMOSedu.com for the future study and discussion.


Discussions & Captured Images:

We need to use the 3 terminal MOSFET symbols different from the tutorial_2. And study how to design the icon of MOSFET. 

1.) To begin, I study the tutorial_2. Follow the design process to make my own tutorial_2. And download C5_models.txt to my lab4 folder. After finishing the tutorial_2, I create a new cell: WWL_LAB4.jelib. Both open the libraries in Electric, use the Cross Library Copy command to copy the NMOS and PMOS cells from my tutorial_2. 

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2.) However, tutorial_2 uses the 4 terminals of MOSFETs as seen below. And the size of MOSFETs are all W=10, L=2.

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3.) Then I delete these MOS symbols and use the 3 terminal ones. And set the charateristics of 10/2 NMOS and 20/2 PMOS. Use Tools--> Simulation (Spice)--> Set Spice Model.. to set the models to NMOS and PMOS. Next I reconnect the nodes and rename them as D, G, and S in both schmatics. Press F5 to check the schematic erros and warnings. The following images are correct.

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4.) Next, design the layouts for these schematics. First, for NMOS layout, select nMOS, nACT, p-well, and Metal1_to_poly1 and put them in the layout cell. The nAct to provide a connection for metal1 Arcs to MOSFET S/D. The Meal1_to_poly1 is used for connecting metal1 to the gate terminal. P-well is to connect the substrate to ground. Second, we need to change the nMos Node's width to 10 and the x-size of nACT and p-well to 10. Then, select nMos Node, go to tools-->Simulation(Spice)-->Set Spice Model... and set the SPICE model name to NMOS(if you don't set we can't simulate the layout.) 

Change x-position of the nMos Node and two nACTs making they align. Use the left mouse select the top port on the nMos Node and right mouse click the nACT. An N-Active was added between the nodes.

The p-well should be put close to S/D node. Next, left click the poly and right click the Metal1_to_poly1 to connect them. We can get the below layout. This is an NMOS layout. 

For PMOS the process is almost the same. Take care that the width is 20 instead of 10. And pMOS, pACT, n-well and Metal1_to_poly1 will be used. The n-well should be connected to vdd. The metal1 node connected to n-well should be named lowercase "vdd".

Finally, we need to name the exports, gate, drain, source. In the tutorial_2, we use lowercase"g,d,s". I change the exports into "G,D,S" and delete the spice code, as shown in the following images. Make sure that DRC, ERC, NCC are passed.

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5.) Then create two new cells to simulate the schematic: sim_NMOS_IV and sim_PMOS_IV. Drag the respective schematic cell into the simulation cells without making icons. Connect a gnd to source node of NMOS(connect vdd to source node of PMOS) and wire arcs are connected to drain and gate with names(they are not exported.)

Put the spice code in the simulation cells and run the simulations to see the results.

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6.) Next, try to make icons for NMOS and PMOS. Go to View--> Make Icon View. Select black point in the components menu. Put one black points in the icon view. Click the black line. Then left click the black point and right click to other place to make a line. Make the NMOS(PMOS) typical symbol as seen below. These three exports should be put in the right position. The PMOS icon also uses the black circle.

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7.) Use the icons to create the another simulation cells. 

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8.) Run the simulation and get the following result. Before simulating the schematic, make sure design has passed DRC, ERC, and NCC.

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Backup the work directory for future study

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