EE 420 Engineering Electronics II and ECG 620 Analog IC Design
Spring 2024, University of Nevada, Las Vegas

   

Current grades are located here.

    

Textbook: CMOS Circuit Design, Layout, and Simulation, Fourth Edition (Chapters 9, 20-24)

Instructor: R. Jacob Baker

Time: MW 1:00-2:15 PM

Course datesWednesday, January 17 to Wednesday, May 1

Location: TBE B-174    

HolidaysMonday, February 19 (President's Day Recess), March 11 and 13 (Spring break from instruction)    

Course contentAn introduction to the design, layout, and simulation of analog integrated circuits including current mirrors, voltage and current references, amplifiers, and op-amps. Credits: 3

Prerequisites: EE 320

 

Grading
20% Test 1 - February 14
20% Test 2 - March 6

20% Test 3 - April 10

40% Final - a single PDF emailed to Dr. Baker at rjacobbaker@gmail.com before Monday, May 6 at 1 PM 

  

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