Homework assignments and Project Information for EE 420 Engineering Electronics II and ECG 620 Analog IC Design, Spring 2017

• Homework guidelines are found here.
• Note that an A in front of the problem indicates an additional problem from the book’s webpage, not a problem from the book’s end–of–chapter problems. A21.34–A21.39

HW#21 – A24.6, due Wednesday, April 26
HW#20 – A24.5, due Wednesday, April 19
HW#19 – A24.1 and A24.4, due Monday, April 17
HW#18 – A23.6–A23.7, due Wednesday, April 5
HW#17 – A22.9 but with the 10 uA current increased to 30 uA, and A23.5, due Monday, April 3
HW#16 – A22.1 and A22.2 but with the 10 uA current increased to 30 uA, due Wednesday, March 29
HW#15 – A21.23 and A21.24, due Monday, March 27

HW#14 – A21.41 and A21.42, due Wednesday, March 22

HW#13 – A21.23, A21.39–A21.40, due Monday, March 20

HW#12 – A21.22, A21.36–A21.38, due Wednesday, March 15

HW#11 – A21.34–A21.35, due Monday, March 6

HW#10 – A20.41, due Wednesday, March 1 

HW#9 – A20.40, due Monday, February 27

HW#8 – A20.39, due Wednesday, February 22

HW#7 – A20.36–A20.38, due Wednesday, February 15 

HW#6 – A9.50–A9.51, due Monday, February 13

HW#5 – Generate a table, similar to Table 9.1 in the book, for general purpose analog design using On's C5 process (process information can be found at On's website, minimum L is 600 nm, SPICE models are found in C5_models.txt). Assume an overdrive voltage of 5% of VDD (= 5V) is used and that an NMOS size of 10/2 (= 6um/1.2um since the scale factor is 600 nm) and a PMOS sixe of 30/2 (= 18um/1.2um) are used, due Wednesday, February 8

HW#4 – A9.48–A9.49, due Monday, February 6 

HW#3 – A9.46–A9.47, due Wednesday, February 1 

HW#2 – A9.43–A9.45, due Monday, January 30  

HW#1 – A9.39–A9.42, due Wednesday, January 25  

Course project – using On Semiconductor's 500 nm process (C5 with two polysilicon layers and 3 levels of metal with a lambda of 300 nm) design a low–voltage op–amp, that is, one can operate with a VDD down to 2 V while driving 10 pF (max) and 1k (min) load. The MOSIS information for this process is located here and the SPICE models are C5_models.txt

Other requirements are:

• DC open–loop gain > 80 dB under all load and VDD conditions
• Gain–bandwidth product should be > 1 MHz
• CMRR > 90 dB at 100 kHz  
• PSRR > 90 dB at 100 kHz
• Slew–rate with maximum load > 1V/microsecond
• Input CMR extends above VDD and below ground
• Output swing within 100 mV of VDD and ground 
  

Your report should detail your design considerations, simulation schematics with results, and provide a table summarizing the results (input CMR as a function of VDD, unity gain frequency, power, slew–rate, etc.) This is not a team effort. A significant portion of your grade will be based on your report. Your report, in PDF, and a zipped–up folder of LTspice simulations (no extra stuff and make it clear what to simulate), should be emailed to rjacobbaker@gmail.com before 4 PM on Monday, May 1. Reports received at 4:01 PM or later will be not be accepted (you will get a 0 on your course project!)  

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