EE 421 Digital
Electronics and ECG
621 Digital Integrated Circuit Design
Fall 2017, University
of Nevada, Las
Vegas
Course lecture
notes and videos are located here
Homework
assignments, due dates, and project information are located here
Current grades are located here.
For the fabrication of chips in this class, On Semiconductor 500 nm, the C5 CMOS process with two polysilicon layers and 3 levels of metal.
The MOSIS scalable CMOS (SCMOS) are found in submicron design rules.
A MOSIS technology
code of SCN3ME_SUBM with a lambda of 300
nm is used with the design rules.
MOSIS information for this process is located here and the SPICE models are C5_models.txt
The Cadence examples from the lectures are found in C5_f17.zip (upload to, and unzip in, $HOME/CMOSedu)
Don't forget to add, to your cds.lib, DEFINE C5_f17 $HOME/CMOSedu/C5_f17 so the Library Manager sees the design directory
Textbook: CMOS Circuit
Design, Layout, and
Simulation, Third Edition (Chapters 16, 1015)
Instructor: R. Jacob Baker (see office hours at
this link)
Teaching Assistant: Sachin Namboodiri
Time:
MW 4:00 to 5:15 PM
Course
dates: Monday, August 28
to Wednesday, December 6
Location: SEB 1242
Holidays: Monday, September 4
(Labor Day Recess)
Final exam time: Monday, December 11, 6 to 8 PM
Course content – An
introduction to the design, layout, and simulation of digital
integrated
circuits. MOSFET operation and parasitics. Digital design
fundamentals
including the design of digital logic blocks. Credits: 3
Prerequisites: CpE
100 and EE 320
Grading
25% Midterm
25% Homework/Quizzes
25%
Course Project (more complicated project for graduate credit, that is,
ECG 621)
25% Final
Policies








1. 
List the main layers used in the fabrication of a digital integrated circuit. Program Outcomes: 1.3, 1.4, 1.6, 1.7, 1.8, 1.9, and 1.10. 
2. 
Sketch the crosssectional view of a layout. Program Outcomes: 1.6, 1.8, 1.9, 1.10, and 1.11. 
3. 
Discuss the movement of electrons and holes in pnjunctions and transistors under various operating conditions. Program Outcomes: 1.1, 1.2, 1.3, 1.6, 1.7, 1.8, 1.9, 1.10, and 1.11. 
4. 
Calculate delays through semiconductor materials and conducting wires. Program Outcomes: 1.1, 1.3, 1.6, 1.7, 1.8, 1.9, 1.10, and 1.11. 
5. 
Describe the operation of MOSFETs using equations and intuitively. Program Outcomes: 1.1, 1.2, 1.3, 1.6, 1.7, 1.8, 1.9, 1.10, and 1.11. 
6. 
Design, estimate delays, and determine speed bottlenecks in digital circuits. Program Outcomes: 1.1, 1.3, 1.6, 1.7, 1.8, 1.9, 1.10, and 1.11. 
7. 
Layout digital circuits and chips. Program Outcomes: 1.3, 1.4, 1.6, 1.7, 1.8, 1.9, 1.10, and 1.11. 
1.1 
An ability to apply mathematics through differential and integral calculus. 
1.2 
An ability to apply advanced mathematics such as differential equations, linear algebra, complex variables, and discrete mathematics. 
1.3 
An ability to apply knowledge of basic sciences. 
1.4 
An ability to apply knowledge of computer science. 
1.6 
An ability to apply knowledge of engineering. 
1.7 
An ability to design a system, component, or process to meet desired needs within realistic constraints. 
1.8 
An ability to identify, formulate, and solve engineering problems. 
1.9 
An ability to analyze and design complex electrical and electronic devices. 
1.10 
An ability to use the techniques, skills, and modern engineering tools necessary for engineering practice. 
1.11 
An ability to design and conduct experiments, as well as to analyze and interpret data. 