Lab 6 - CMOS NAND Gate

Lab 6 - ECE 421L

Authored by Brandon Staffieri

staffier@unlv.nevada.edu

October 06, 2021

Lab Description

Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder

Prelab Content

Prior to this lab session, we were tasked with backing up our previous work (as usual) as well as finishing Tutorial 4, in which we learned how to design, layout, and simulate a CMOS NAND gate. We were also tasked with giving the entire lab document a quick read through in preparation of the actual lab.

CMOS NAND Gate Schematic:

CMOS NAND Gate Symbol:

Simulation Schematic Utilizing CMOS NAND Gate Symbol:

ADE Simulation Settings:

Transient Response Graph:

CMOS NAND Gate Layout:

DRC Clean:

Extracted View:

LVS Settings:

LVS Clean:

Postlab Report

For the main portion of this lab, we were tasked with drafting the schematics for a 2-input NAND gate and 2-input XOR gate using 6u/0.6u MOSFETs. This involved creating the layout and symbol views, along with providing proof of DRC and LVS verification. Though we created a 2-input NAND gate in the prelab portion of this lab, it did not follow all of the newly added guidelines shown below, so it had to be redone.

The new guidelines are as follows

Ensure that your symbol views are commonly used symbolds for these gate with your initials in the middle of the symbol
Ensure all layouts in this lab use standard cell frames that snap together end-to-end for routing vdd! and gnd!
Use a standard cell height taller than you need for these gates so that it can be used for more complicated layouts in the future
Ensure gate inputs, outputs, vdd!, and gnd! are all routed on metal1

The images documenting the 2-input NAND gate can be seen as follows:

2-Input NAND Gate Schematic (Unchanged From Prelab):

2-Input NAND Gate Schematic (Updated With My Initals):

2-Input NAND Gate Layout (Updated to Extend the Height of the Layout and Adjust MOSFET Width):

DRC Clean:

2-Input NAND Gate Extracted Layout (Updated with the Extended the Height of the Layout and Reduced MOSFET Width):

LVS Settings (Also Showing Updated Cell Name With Initials and Current Semester):

LVS Clean:

Now that the 2-input NAND had been updated to fit the new parameters, the next step was to draft the 2-input XOR gate.

The images documenting the 2-input XOR gate can be seen as follows:

2-Input XOR Gate Schematic:

2-Input XOR Gate Symbol:

2-Input XOR Gate Layout:

DRC Clean:

2-Input XOR Gate Extracted Layout:

LVS Settings:

LVS Clean:

Now that both the 2-input NAND and 2-input XOR gates had been drafted and verified through both DRC and LVS, the next step was to place the newly created NAND and XOR gates along with our Inverter that we created earlier in Lab 5 into one schematic in order to simulate all possible combinations of inputs (being 00, 01, 10, and 11). To ensure that all 4 inputs were shown, I offset the period of the B input such that A is 40ns and B is only 20ns.

Simulator Schematic:

Transient Simulation Results (RAW):

One thing to note in these transient simulation results is that at moments when all of the input pulses transition at once, the output can sometimes appear glitchy (mostly observable for AxorB in this case). This is because in a real circuit, logic signals cannot instantaneously switch from on-to-off or vice versa. To represent this, in this simulation, the pulse sources were given a 1n rise and fall time. As these signals transition from between logic high and logic low, the MOSFETs in the gates have a delay when switching on or off and that delay can cause a brief moment of unpredictable behaviour.

In order to better convey how the above transient simulation results verify the operation of the circuits, I will include the following truth tables for NAND, XOR, and Inverter gates alongside an edited version of the simulation results image that displays all of the logic values.

NAND

XOR

Inverter Truth Table

As can be observed above, for each of the gates' respective truth tables, the simulation results hold true, and thus the operation of all gates is successfully verified.

Now, for the much more involved portion of this lab, we needed to use the gates that we just created in order to draft a schematic for a full adder. Then, we created a symbol for this schematic, and utilized that to perform a transient simulation to verify the operation of our circuit.

Full Adder Schematic:

Full Adder Symbol:

Full Adder Simulation Schematic:

Full Adder ADE Spectre Simulator Settings:

Full Adder Simulation Results (RAW):

In order to better convey how the above transient simulation results verify the operation of the circuit, I will include the following truth table for a Full Adder circuit alongside an edited version of the simulation results image that displays all of the logic values. This truth table was pulled directly from the Lab 6 document.

As can be observed above, the circuit simulation is working perfectly and thus verifies the operation of my Full Adder. The next step was to layout the full adder by placing 5 of the newly created gates (3 NAND and 2 XOR). Additionally, as with all other layouts, the full adder layout was verified to be DRC and LVS clean.

Full Adder Layout:

DRC Clean:

Full Adder Extracted Layout:

LVS Settings:

LVS Clean:

Backup

My online backup of my completed files can be downloaded here.

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