Lab 5 - ECE 421L
Design, layout, and simulation of a CMOS inverter
Prelab Content
Prior to this lab session, we were tasked with backing up our previous work (as usual) as well as finishing Tutorial 3, in which we learned how to design, simulate, and layout a CMOS inverter.
Postlab Report
This lab consisted of modifying the CMOS inverter than we created in the prelab, and simulating under varying capacitive loads in multiple simulators.
The first step of this lab was the most simple. We were tasked with drafting a schematic, layout, and symbol for a 12u/6u (PMOS width/NMOS width) CMOS inverter. As we had already drafted these for the Prelab, all we had to do for this step was simply adjust the symbol to contain a label indicating the PMOS and NMOS device widths. As such, I have only included an image of the modified symbol for this step. All the other items can be found in the 'Prelab Content' section above.
This next step was more involved, as we had to modify all items such that our PMOS and NMOS widths were now 48u and 24u respectively by using a multiplier of 4 on our previous design. The updated items can be seen as follows:
Now that both the 12u/6u and 48u/24u CMOS inverters had been fully implemented, the next step was to use SPICE to simulate each of them driving a 100fF, 1pF, 10pF, and 100pF capacitive load. This first round of simulations was performed using the 'spectre' simulator.
The 12u/6u 'spectre' simulation schematic, simulation settings, and transient response graphs (with parametric analysis to adjust the capacitive load) can be seen here:
The 48u/24u 'spectre' simulation schematic and transient response graphs (using identical simulation settings and parametric analysis to adjust the capacitive load) can be seen here:
Lastly, we were tasked with running these simulations again under identical conditions; however, this time the simulator was switched from 'spectre' to 'UltraSim'. UltraSim is Cadence's fast SPICE simulator primarily used for larger circuits, though this increase in speed comes with a decrease in accuracy (along with the fact that 'UltraSim' can only perform transient simulations). Though, as can be observed in the following images, this decrease in accuracy is almost completely imperceptible for our specific case.
The 12u/6u 'UltraSim' transient response graphs (using identical simulation settings and parametric analysis to adjust the capacitive load) can be seen here:
The 48u/24u 'UltraSim' transient response graphs (using identical simulation settings and parametric analysis to adjust the capacitive load) can be seen here:
Backup
My online backup of my completed files can be downloaded here.