Digital Integrated Circuit Design

EE 421L - Fall 2021

Lab 7

Author: Ryan Eclarinal

Email: eclarina@unlv.nevada.edu

Date Assigned: October 20, 2021

Due Date: November 3, 2021

Pre-Lab:


 Create a new schematic cell and place an inverter.

   
Highlight the inverter and press the bindkey c(copy), and put 30 under columns to place 31 inverters on the cell.

   
Now, connect the end of the last inverter to the input of the inverter with wire and label it osc_out.

    

We are ready to simulate the design by putting the correct parameters.

Here, we need to select the initial condition.

    

Setting up the Analog Stimuli

    

Result of the simulation:

      

Now, we need to modify our schematic to look neat using an array. Using bindkey shift+W will create a wide that is place to the input and output of the inverter. We also need to label the wire as seen below.

     

Running the simulation again will give the same results.

    

After creating the schematics, we need to create a layout view of the ring oscillator. Instantiate 31 inverters from the previous lab and connect it with metal1 and add some necessary pins. DRC the design to make sure that there is no errors.

    

Layout view:

    

Extracted view:

    

LVS showing that the net-lists didnt matched.

    

We need to fix the schematics by adding a small wire in between the pin and the wide wire and label it osc_out.

    

Rerunning the LVS again and this time it shows that the net-lists matched.

    

    

Now, we need to create a symbol for our ring oscillator.

    

Creating the schematic to simulate the design.

    

Setting up the initial condition:

    

Results:

    

Showing the output log that we were running the schematic view.

   

This concludes the Prelab.

        

____________________________________________________________________________________________________________

Lab 7 - Using buses and arrays in the design of word inverters, muxes, and high-speed adders

Lab Procedure:

Create schematics and symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR gates.
Provide a few simulation examples using these gates.
Next examine the following schematic.
This is the schematic of a 2-to-1 DEMUX/MUX (and the symbol).
Simulate the operation of this circuit using Spectre.
Create an 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol.

Finally, draft the schematic of the full-adder seen in Fig. 12.20 using 6u/0.6u devices (both PMOS and NMOS).
Create an adder symbol for this circuit.
Use this symbol to draft an 8-bit adder schematic and symbol.

Simulate the operation of the 8-bit adder. 
Lay out this 8-bit adder cell (*note* that this is the only layout required in this lab).
Show that the layout DRCs and LVSs correctly.

    

   

Experiment 1: Creating a 4-bit word inverter

   
Creating a copy of my previous lab to a new library and named it lab7_re.

   

We need to create a new cell for the inverter and create a schematic.

    

Symbol of the inverter:

    

Create a new cell for the 4-bit inverter.

    

Schematic of the 4-bit inverter

    

Symbol:

    

Creating a new schematic for simulation:

    

Putting the parameters:

    

Opening the ADE and simulate the design.

    

Result of the simulation:

    

Out<0> has no load, therefore, it shows that the rise and fall times are fast.

Out<1> has the big capacitor load giving it a higher RC time delay.

We can say the same thing to the other outputs.

   

   

Experiment 2: Creating a NAND gate/ 8-bit Input/Output array of NAND gate

   
Schematics of a NAND gate:

    

Symbol of the NAND gate:

   

Schematic of the 8-bit NAND gate using an array and wide wires.

    

Symbol of the 8-bit NAND gate

    

Schematics of the 8-bit NAND gate to use for simulation.

    

Results of the simulation:
For A        a<7:0> = 10101010
NAND B   b<7:0> = 00110011
aNANDb   =            11011101

   

    

Experiment 3: Creating a NOR gate/ 8-bit Input/Output array of NOR gate

   
Schematics of a NOR gate:

       

Symbol of the NOR gate:

   

Schematic of the 8-bit NOR gate using an array and wide wires.

    

Symbol of the 8-bit NOR gate

   

Schematics of the 8-bit NOR gate to use for simulation.

    

Results of the simulation:
For A        a<7:0> = 10101010
NOR B      b<7:0> = 00110011
aNORb   =             01000100

    

   

Experiment 4: Creating an AND gate/ 8-bit Input/Output array of AND gate

     
Schematics of an AND gate:

    

Symbol of the AND gate:

    

Schematic of the 8-bit AND gate using an array and wide wires.

    

Symbol of the 8-bit AND gate

    

Schematics of the 8-bit AND gate to use for simulation.

    

Results of the simulation:
For A         a<7:0> = 10101010
AND b       b<7:0> = 00110011
aANDb   =              00100010

    

   

Experiment 5: Creating an OR gate/ 8-bit Input/Output array of OR gate

   
Schematics of an OR gate:

    

Symbol of the OR gate:

    

    

Schematic of the 8-bit OR gate using an array and wide wires.

    

Symbol of the 8-bit OR gate

    

Schematics of the 8-bit OR gate to use for simulation.

    

Results of the simulation:
For A       a<7:0> = 10101010
OR B        b<7:0> = 00110011
aORb   =                 10111011

   

Experiment 6:  Creating an 8-bit Input/Output array of inverter

   
Schematic of the 8-bit inverter using an array and wide wires.

    

Symbol of the 8-bit inverter

   

Experiment 7: Creating a 2-to-1 DEMUX/MUX

    

Schematics:

    

Symbol: We placed 1 and 0 to show the user what to do with the select S input.

    

Schematics of the 2-t0-1 DEMUX/MUX to use for simulation.

    

Result of the simulation:

If we send 1 to S, it selects the input A and outputted into Z.

If we send 0 to S, it selects the input B and outputted into Z.

   

   

Experiment 8:  Creating an 8-bit Word 2-to-1 DEMUX/MUX

   

Creating the schematics by laying out 8 symbols of the 2-to 1 demux.

    

Results of the simulation:

   

   

Experiment 9: The Full-Adder and Creating an 8-bit Adder

   

Schematics of the Full-Adder:

    

Symbol:

    

Schematics of an 8-bit-Adder:

    

Results of the simulation:

    

Layout view of the 8-bit Full-Adder:

    

Extracted view of the 8-bit Full-Adder:

    

DRC showing no errors:

    

LVS showing that the net-lists matched.

    

   

    

Backing up:
    
Perform a regular back up of my work by making a zip file and upload it to my Google Drive.

   

 

This concludes Lab 7.

    

   

Return to Students

Return to EE 421L

Return to CMOSedu.com