Lab
3 - EE 421L
Prelab:
- Back-up all of the previous work.
- Finish Tutorial 1 seen here.
%%% Click here to download lab3.zip %%%
Lab report: Layout of the 10-bit DAC you designed and simulated in Lab2.
- Use the n-well to layout a 10k resistor as discussed in Tutorial 1.
How to select the width and legnth of the resistor?
- For the fabrication of chips in this class, C5 (500nm) CMOS prcoess is used.
- Design rule of MOSIS scalable CMOS are found here.
- A MOSIS technology code of SCN3ME_SUBM with a lambda of 300 nm is used.
A lambda (λ) is the unit of measurement, which can be scaled to different fabrication processes as semiconductor technology advances.
One lambda (λ) in our process is 0.3 microns or 300 nm. (see table below for reference)
Rule is specified in unit of lambda (λ). (see table below for important rules)
We can see from table above that the minimum width of the N-well is 12λ
Our process of 1 λ is 0.3 µm, so we can calculate minimum length N-well is
12 * 0.3 µm = 3.6 µm
We know the minimum length is 3.6 µm.
However, one impoortant rule to consider is you need to be 'on grid' in cadence.
You can check your grid spacing by pressing bindkey 'e' or go to 'options -> Display'
You can see from figure above that grid snap spacing is 0.15 or half of a lambda (λ),
meaning your length and width must be divisible by 0.3 and by 0.15 in order to be on the grid, if not, you'll get an error.
Tutorial 1 used minimum width of 4.5 µm because 2 rows of ntap has the same size.
Use the following equation to find the length.
where R square in the C5 process is approximately equal to 800Ω/square
information of C5 process is found here (or see table below).
Our task is to layout a 10kΩ resistor.
using the equation above,
10kΩ = 800Ω/square * (length/4.5 µm) ==> length = 56.25 µm
56.25 is divisible by 0.15 but it's not divisible by 0.3,
hence you must round up or down to be on grid.
In our case, we round down to 56.1, which is divisible by 0.15 and 0.3.
By following Tutorial 1 closely, you can layout a 10kΩ n-well resistor by drawing
4.5 µm x 56.1 µm n-well square and attach 'n-tap' cell to both ends of the square, attach 'L', 'R' Pins,
and draw a 'res_id' on top of 4.5 µm x 56.1 µm n-well square and you get the following cell:
After you successfully run DRC (design rule check) of the cell, you can extract the cell and get the following:
If you zoom in a little closer, you can see that the cell has value of 10.21kΩ (see image below).
Is 10.21kΩ acceptable? Yes, the sheet resistance of n-well varies by the process and manufacturing process varies so you can't get a precise resistance of 10kΩ.
- Use this n-well resistor in the layout of your DAC.
After you have a 10kΩ resistor cell, you need to create a voltage divider layout.
You could layout a DAC without having a separate voltage divider layout,
but it is much easier going this route, much less troubleshooting and a good practice in general.
Using the schematic and the symbol created in lab 2 (see figures below), layout a voltage divider cell.
You can layout a voltage divider cell simply by following the Tutorial 1.
First, instanciate 3 resistors in parallel,
and name the pins same as schematic (be sure to select the same I/O pin as schematic, if not, netlist won't match)
and connect the resistors by using metal 1.
You need keep in mind the minimum distance between two n-well is 18 λ or 5.4 µm.
In Tutorial 1, we used spacing of 7.5 µm or 12 µm on center for convenience.
(layout of voltage divider cell)
(extracted layout of voltage divider cell)
DRC the layout and then extract the cell and run LVS (layout vs. schematic).
Once you have a voltage divider cell that had a successful run of LVS, you can now layout a DAC by referencing the schematic and the symbol seen below:
When layingout DAC, ensure that each resistor in the DAC is laid out in paralel having the same x-position but varying y-position
and all input and outputs Pins should be on metal 1. DRC and LVS, with the extracted layout.
First, create a layout cell that contains schematic and symbol, and instantiate 10 voltage divider cell (10 bits) and a single 10k resistor,
name the pin(s) same as schematic and connect the pins by using metal 1.
I used 'path' instead of drawing multiple 'rectangles' of metal 1 to connect between pins.
Here is the layout and extracted view of the DAC:
(Click on the images below to zoom in and see the layout in full detail)
(use the mouse scroll wheel to go up/down and press shift and mouse scroll wheel to go left/right)
Run DRC and LVS of the DAC:
Run simulation using extracted cell results (same plot from lab2):
Notice that the view name of Mydesign_10bit_DAC is pointing to the extracted
- Zip up your final design directory and place it in the lab3 directory.
Click here to download lab3.zip