Lab 2 - EE 421L 

Authored by Peter Kim

kimj98@unlv.nevada.edu

9/9/2020

Prelab:

-  Read through the entire lab2.

-  Simulate the cell sim_Ideal_ADC_DAC.

-  Understand how the input voltage, Vin, is related to B[9:0] and Vout.

-  Provide narrative of the simulation.

-  Discuss, using simulations to illustrate your understanding of ADC and DAC.

-  Explain how you determine the least significant bit (LSB)

-  Backup your webpages and design directory.

Prelab Report:

Download lab2.zip to your desktop and upload to your CMOSedu folder and unzip the file.
Be sure to update the 'cds.lib' by using following statement.
(DEFINE lab2 $HOME/CMOSedu/lab2)


Start Cadence and verify you have access to lab2 files in the library manger.


open the schematic view of the cell sim_ideal_ADC_DAC


Run simulation using ADE L

         The resolution of 10-bit DAC is 2^10 = 1024

         Calculate the LSB by using the following equation:

        where N is the number of bits (10 bits) and VDD is given (5V)

        Simulations to understand DAC and ADC

        Case 1: digital value input is 0000000001


        The output is 4.88mV, which corresponds to LSB.

       Case 2: digital value input is 1000010001

       The output is 2.58V.

      Case 3: amplitude of Vin is equal to LSB

Output: each step shows difference of 488mV

Back up the work by zipping the folder keep a copy in my email folder.

Lab Report:

-   Design of a  10-bit DAC using an n-well R of 10k

   First, create a schematic for 2R_R block and create a symbol for the schematic

        then, create a schematic for 10-bit DAC and create a symbol using the 10-bit ideal DAC symbol deleting unused pins

Finally, replace new 10-bit ideal DAC by 10-bit MY DAC, check and save the new schematic 

run the simulations and match the result with ideal 10-by DAC from prelab.

-   How to determine the output resistance of the DAC (answer: R) by combining resistors in parallel and in series.

    (from the bottom bit, the equivalent resistance is 2R // 2R = R, and R+R = 2R, repeat the process to get output resistance of DAC)

-   Delay, driving a load (ground all DAC inputs except B9, connect B9 to a pulse source and predict the delay with 10pf load)

     td = 0.7RC, where R=10k, C=10pf, td = (0.7)(10k)(10p) = 70ns (Hand calculation matches with simulation)

     1 LSB = VDD/2^N = 5/2^1 = 2.5V (time delay is calulated at half of the input which is 2.5/2 = 1.25V)

-   Show simulations to verify your design functions.

Driving a 10K load (output magnitude cut in half, in phase with input)

Driving a 10pf load (output is delayed and smooth out curves)

Driving a 10K and 10pf load (output magnitude is cut in half and delayed)

    Discuss what happens if the resistance of the switches isn't small compared to R.

            -   If the resistance of the switche is close to R, it'll act as an extra resistor creating 3R_R voltage divider resulting in lower output voltage.

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