Lab 7 - EE 421L - Fall 2019
Using Buses and Arrays in the Design of Word Inverters, Muxes, and High-Speed Adders
Authored
by John Patrick Buen
Rebelmail: buenj1@unlv.nevada.edu
11/5/2019
Prelab: The prelab for this lab is to complete Tutorial 5. Images for the tutorial are shown below.
Ring Oscillator: schematic, layout, extracted view, and simulation
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LAB:
1. Design and Simulation of 4-Bit Inverter
Originally, the 4-bit inverter is designed as shown below.
To
have an equivalent and concise schematic for the 4-Bit Inverter, I used
wide buses/wires to connect the input and output pins. (wide wires can
be used by doing the shift+W bindkey)
Schematic
Symbol
->
The
inverter shown in the above schematic must also have it's instance name
be edited (bindkey Q) to perform a multiple bit operation. In this
case, I named the instance of the inverter IO<3:0> operating
4-bits. The instance name is displayed as a 'value'.
Simulation of the 4-Bit Inverter:
Simulation Schematic and Simulation
The output of the 4-bit inverter is driven with multiple
capacitive loads (100fF, 500fF, and 1pF). out<0> does not have a
load.
Simulation
According
to the simulation above, driving a capacitive load influences the delay
and the rise/fall times of the output signals. The trend shown above is
that the higher the magnitude of the capacitive load, the slower the
rise/fall
times
of the signal. Not having a load capacitor or having a very small
capacitive load on the output would account for the opposite in which
results to rise/fall times being much sharper and faster.
2. Design and Simulation of an 8-Bit NAND, NOR, Inverter, AND, and OR Gates
- Design of an 8-Bit NAND Gate:
The NAND gate used in the following schematic for the 8-bit NAND was the NAND gate used in Tutorial 4.
1-Bit NAND Schematic and Symbol
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8-Bit NAND Schematic and Symbol
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- Design of an 8-Bit NOR Gate:
1-Bit NOR Schematic and Symbol
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8-Bit NOR Schematic and Symbol
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- Design of an 8-Bit AND Gate:
1-Bit AND Schematic and Symbol
->
For
the AND schematic, I simply inverted the output of a NAND gate to have
an AND operation. (AND is just the inverse/complementary function of
NAND)
8-Bit AND Schematic and Symbol
->
- Design of an 8-Bit Inverter:
The design for the 8-bit inverter is composed of instantiations of the 1-bit inverter that was previously made.
8-Bit Inverter Schematic and Symbol
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- Design of an 8-Bit OR Gate:
1-Bit OR Schematic and Symbol
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Again
like the AND gate, I also inverted the output of the NOR gate to make
the OR gate. (OR is the inverse/complementary function of the NOR)
8-Bit OR Schematic and Symbol
->
Schematic and Simulation Results of ALL the Gates:
Simulation
For
the simulation schematic, all of the inputs of all 8-bits for each gate
have the same input signal corresponding to their respective A and B
pins. Shown in the simulation above, I only showed bit<0> for the
outputs of the 8-bit NAND, NOR, AND, and OR gates since all of the
output bits output the same signal.
3. Design and Simulation of a DEMUX/MUX
The schematic and symbol for the MUX is shown below (given schematic)
-> 
The
function of the DEMUX/MUX shown above is for multiplexing only because
the inputs A and B are designed to have a connectivity that is 'input'
only. Same thing goes for the output Z, it's connectivity is 'output'
only. Thus the operation of the above schematic goes in only one
direction where the select input (S) controls which input (A or B) to
output onto Z.
In
order to have the schematic operate as either a DEMUX or MUX, the
inputs (A and B) and output (Z) pins have to have a connectivity of
'input/output' so that the operation can go both ways. For example,
to operate as a MUX, the select input (S) will select either A or B to
output depending if S is low or high (logic 0 or 1). In this case, A
and B are inputs and Z is an output. To operate as a DEMUX, the select
input will select where to output Z depending if the select is either
low (output to B) or high (output to A). In this case, Z is an input,
and A and B are outputs.
New Schematic and Symbol for the DEMUX/MUX (A, B, and Z pins are changed to input/output)
->
Simulation
Schematic for the DEMUX/MUX (the DEMUX/MUX is instantiated twice in
order to simulate both the DEMUX and MUX operations)
Simulation of the DEMUX/MUX
Design and Simulation of an 8-Bit DEMUX/MUX:
8-Bit DEMUX/MUX Schematic and Symbol
->
From
the schematic above, the Si select input is inverted from the S select
input. This is because the Si input is just an inversion of the select
signal S and by doing this, there is now only 1 select input for the
DEMUX/MUX.
Simulation Schematic for the 8-Bit DEMUX/MUX and Simulation
Simulation
The
simulation for the 8-bit DEMUX/MUX is the same for the 1-bit DEMUX/MUX
because I only displayed 1 bit for each of the input and outputs on the
simulation.
Design and Simulation of an 8-Bit AOI (High-Speed) Full Adder:
Schematic of a 1-Bit AOI Full Adder (from the book)
Symbol
Layout of the AOI Full Adder
Extracted View
DRC and LVS Result of the 1-Bit AOI Full Adder
The 1-Bit AOI Full Adder DRC'ed and LVS'ed successfully.
Schematic of the 8-Bit AOI Full Adder
The
notation of the wide wires on the Cin and Cout pins are inspired by the
ring oscillator wide wire notation in the prelab. Besides the first Cin
and the last Cout
bits, each cin of each bit of the 8-Bit Full
Adder would be the cout of it's preceding full adder. In summary, the
Cin bit would ripple through all 8 Full Adders
towards the very last Cout bit.
Symbol of an 8-Bit AOI Full Adder
Layout of an 8-Bit Full Adder
Extracted View
DRC and LVS Results of the 8-Bit Full Adder
The 8-Bit AOI Full Adder DRC'ed and LVS'ed successfully with no errors.
Simulation Schematic for the 8-Bit AOI Full Adder
To
test the operation of the 8-Bit Full Adder, I wanted to test 4 + 4
(00000100 + 00000100) which equals 8 or 00001000. With the Cin bit = 0.
Simulation Result
The
simulation above only shows the output sum (Z) from the simulation
schematic. The result shows only bit <3> to be high and the rest
of the bits are low. This
is
the correct result from the addition since 4 + 4 = 8 where 8 is
equivalent to 00001000 proving that only bit <3> is high.
Project Zip File: lab_7.zip
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