Project: 9-bit Even Parity Checker - EE 421L 

Authored by Andy Sam,

sama1@unlv.nevada.edu

11/15/2017

The project for this class is creating 9-bit even checker using the C5 CMOS proccess. The circuit inputs 8 data bits and 1 parity bit, then outputs an even check bit.

The XOR gate:

The basis for the parity checker is the XOR gate. Logically, a 2-input XOR gate can be defined as a gate that goes high when the inputs are not equal and goes low when they are.

The following truth table describes this logic:

We can use this logic to check whether the two inputs add up to an even number or an odd number. If the inputs are both the same, we have an even number of bits "High" (zero inclusive). If both are different, then we have one bit "High" (therefore an odd number of bits high). This logic will be further elaborated to fully form the parity checker.

XOR gate at the transistor level (see Lab 6 for further detail):

In the parity checker design, we will need an inverter. An inverter simply turns a "high" input to a "low" output or a "low" input to a "high" output. This inverter is used at the end of the design so we get a proper "error" signal from our logic when we do have an even number of bits. We will be using the 12u/6u inverter created in Lab 5.
       
12u/6u inverter schematic and symbol:

The Parity Checker:

From the XOR gate, we can create our 9-bit parity checker. As from before, each XOR gate checks if there is an even or odd number of bits in a pair. If there is an odd number of bits, a "high" is produced. If there is an even number of bits, a "low" is produced. After the first stage of XOR gates, the next stage of XOR gates also check for the number of even or odd bits. If there is an odd number of bits from one of the previous stages before and if there is an odd number of bits from the other stage, we produce a "low". This is because an odd number of bits added to another odd number of bits is even. This same thing applies when an even number of bits add up with another even number of bits. Cascading this logic together at multiple levels, we get an even bit pairty checker that outputs a "high" if there is an even number of bits and "low" if there is an odd number of bits. The 8-bit input is arranged in this cascading arrangement, and the final stage is XOR'd with the parity bit. Because we want a "high" when there is an even amount of bits to indicate "valid", we add an inverter to the final stage of the XOR gate schematic.  

If the parity bit is "high" and the other 8 bits are even, we output a "high" to the inverter. This ultimately gives us a "low" for the check. This means there was an error and the parity check is not valid. The same principle applies when the parity bit is "low" and the input is odd. On the other hand, if there was a "high" on the parity bit and the other 8 bits are odd, the check will output a "high" indicating no error in the check. The same thing applies when the parity bit is "low" and the input is even. 

Of course, one weakness of the parity checker is that if there are an even number of input errors, then we do not detect an error. Another major flaw in the parity checker is if we would not be able to pinpoint which input contains the error in transmission.

Parity Checker Schematic:

Note that every input has twice the period of the next pulse input, therefore we get every possible combination of signals in the simulation. The smallest pulse period starts at 10ns with a 50-50 duty cycle.

Parity Checker Simulation with Parity Bit High (left) and Bit Low (right):

As we can see from the results of the parity bit checker simulation, when there are an even number of bits on in the input (including the parity bit), the output bit swings to a digital "high" of 5V. When there is an odd number of bits on, the output swings "low" to 0V. Note that there is roughly a 1.5ns propagation delay between the inputs and the final output.

The Parity Checker Layout:

DRC:

LVS:

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