Lab 6 - EE 421L 

Authored by Andy Sam,

sama1@unlv.nevada.edu

10/25/2017 

In lab 6, we create a CMOS NAND gate and XOR gate in both schematic and layout. After they are created, a full adder is created from the 2 gate types.

LVS of NAND gate:

Schematic of XOR gate:


DRC of XOR gate:


LVS of XOR gate:

Schematic of simulation test circuit (with created symbols):


Simulation results:

As we can see from the simulation results, on rising edges or falling edges of the inputs, we can get glitches on the outputs where the output voltages tend to bounce very high or low for a small moment.

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Schematic of full adder:

Symbol for Full Adder:

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