Lab 6 - ECE 421L 

Authored by Byron Gorsuch,

gorsuch@unlv.nevada.edu,

10/25/2017 

This lab demonstrates how to draft schematics, layouts and symbols for a 6μ/.6μ nand gate, a 6μ/.6μ xor gate. Using the nand and xor gates, a layout and schematic for a full adder is then created. 

Prelab

    Tutorial 4 was followed in order to create a schematic and layout for a nand gate.

                                            Figure 1: NAND2 Schematic                                        Figure 2: NAND2 Layout      Figure 3: NAND2 Extracted                               Figure 4: NAND2 Symbol

                                                         Figure 5: DRC Results for NAND2 Prelab Layout                                                             Figure 6: LVS Results (FAIL) for Prelab

    As can be seen in figure 6, the LVS did not succeed because the layout used 12μ/6μ MOSFETS which did not match the 6μ/.6μ schematic.

Lab Work

    In order to fix the LVS issue from the prelab, the layout for the 2 input NAND gate was modified as follows:

                       
Figure 7: Correct NAND2 Layout     Figure 7: Correct NAND2 Extracted                                                                   Figure 8: NAND2 LVS Success

As can be seen, now the LVS matches and we can proceed with the creation of a two input XOR gate. Furthermore, the updated layout is in a standard frame which will make laying out the XOR and

future layouts simpler.

By using the two input NAND gate above, and the inverter (Lab 5), modified to be 6μ/.6μ, a two input XOR can be created as follows:

                                    Figure 9: XOR2 Schematic                                                                            Figure 10: XOR2 Layout                                                           Figure 11: XOR2 Extracted

                               Figure 12: XOR2 Symbol                                                                        Figure 13: XOR2 DRC                                                                            Figure 14: XOR2  LVS

In order to ensure the gates that have been created work as intended, the following schematic was used in order to test the responses of the schematics:

                                            Figure 15: Gate Testing Schematic                                                                                                                 Figure 16: Results of Gate Test Simulation

As can be seen in the simulation, if the rise/fall of the inputs occurs around the same time, there is a jutter in the output signal. The timing of the input signals must be long enough for the gates to process.

Since the gates work as expected, they can be put together to create a full adder.

                                          Figure 17: Full Adder Schematic                                                                                                               Figure 18: Full Adder Layout

                                       Figure 19: Full Adder Extracted                                                                  Figure 20: Full Adder DRC                                                  Figure 21: Full Adder LVS

                 Figure 22: Full Adder Symbol                                                    Figure 23: Full Adder Simulation Schematic

The schematic seen in figure 23 above was used in order to simulate the full adder. The following waveforms are the result:
   

                                          Figure 24: Full Adder Reasonable Timing                                                                                                Figure 25: Full Adder Fast Timing

Figure 24 shows the inputs and outputs of the full adder when given inputs with reasonable frequency, about 100 ns. As can be seen the results are as expected although there are some spikes where the two inputs change at the same time.

Figure 25 shows the inputs and outputs of the adder where the input frequency is much too fast for the circuit to process, and thus the outputs become more rounded and inconsistent.

A zip folder of this lab can be found HERE

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