Lab 7 - EE 421L 

Authored by Staford Snow, snows4@unlv.nevada.edu

11/15/2016

  

Lab description:

In this lab, I learned about utilizing buses and arrayed symbols in our designs to make schematics concise and easier to use.  I then used the buses and arrayed symbols to create 8-bit gates including: NAND, NOR, AND, OR, and inverter.  Afterwards I created an 8-bit wide word 2-to-1 DEMUX/MUX and full adder.

 

Pre-Lab:

Following the lab instruction, I backed up all my work from the lab and course, read through the entire lab, and went through Tutorial 5.

 

Lab:
To start the lab, I followed the instructions for how to create a 4-bit inverter.  First, I created a the schematic and symbol for a 6u/6u inverter.

 

6u_inverter_sds_f16_schematic.png  6u_inverter_sds_f16_symbol.png

 

I then used an array of this symbol to draft a schematic and symbol for the 4-bit inverter.

 

4bit_inverter_sds_f16_schematic.png  4bit_inverter_sds_f16_symbol.png

 

After finishing the 4-bit inverter, I set up a schematic to simulate the operation of the inverter.

 

sim_4bit_inverter_sds_f16_schematic.png

 

This simulation circuit generated the following graphical output:

 

sim_4bit_inverter_sds_f16_graph.png

 

The varying capacitive loads on the inverter changes the switching delay of the inverter.  As the capacitive load increases, the rise/fall time increases proportionally.

 

After creating and simulating the 4-bit inverter, I began the design of the 8-bit NAND, NOR, AND, OR, and inverter.  I adjusted the process I had just learned to be used to create 8-bit gates.

 

I combined these 8-bit gates into one schematic to simplify simulation.

 

sim_8bit_gates_sds_f16_schematic.jpg

 

After simulation, I derived the following graphical output:

 

sim_8bit_gates_sds_f16_graph.jpg

 

The next schematic and symbol I was instructed to draft was of a 2-to-1 DEMUX/MUX.

 

2_1_mux_demux_sds_f16_schematic.png  2_1_mux_demux_sds_f16_symbol.png

 

I created the following schematic to simulate multiplexing:

 

sim_2_1_mux_sds_f16_schematic.jpg

 

Which gave this graphical output:

 

sim_2_1_mux_sds_f16_graph.jpg

 

To simulate de-multiplexing, I drafted this schematic:

 

sim_2_1_demux_sds_f16_schematic.jpg

 

Which produced this output:

 

sim_2_1_demux_sds_f16_graph.jpg

 

The DEMUX/MUX works by setting the S/Si inputs to either decide whether input A or B is let through to Z while MUX-ing, or to select whether Z will output to A or B while DEMUX-ing.

 

I next created an 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol.  I included an inverter in my schematic to the finished cell only needs one select input.

 

8bit_2_1_mux_demux_sds_f16_schematic.png  8bit_2_1_mux_demux_sds_f16_symbol.png

 

I then drafted a schematic to perform simulation of the 8-bit wide word DEMUX/MUX.

 

sim_8bit_2_1_mux_sds_f16_schematic.jpg

 

The simulation generated the following graphical output:

 

sim_8bit_2_1_mux_sds_f16_graph.jpg

 

The final part of the lab was to draft the full-adder schematic shown in Fig. 12.20 in the book.  I was instructed to use 6u/0.6u sizes for both the PMOS and NMOS.

 

fig12_20_fa_sds_f16_schematic.png

 

I then created a symbol to represent this schematic.

 

fig12_20_fa_sds_f16_symbol.png

 

I made an array of this symbol to represent an 8-bit full-adder in a schematic and symbol.

 

8bit_fig12_20_fa_sds_f16_schematic.png  8bit_fig12_20_fa_sds_f16_symbol.png

 

I labeled the buses on cin and cout to loop.  Cout of the first full-adder was connected to cin of the second full-adder and so on for all 8 full-adders.

 

I created a schematic to simulate the 8-bit full-adder.

 

sim_8bit_fig12_20_fa_sds_f16_schematic.jpg

 

After simulating, I was able to verify the 8-bit full-adder worked correctly.

 

sim_8bit_fig12_20_fa_sds_f16_graph.jpg

 

Lastly, I created a layout of the 8-bit full-adder.

 

8bit_fig12_20_fa_sds_f16_layout1.png

 

A closer view of each individual full-adder is below:

 

8bit_fig12_20_fa_sds_f16_layout2.png

 

This layout successfully passed DRC and LVS.

 

8bit_fig12_20_fa_sds_f16_drc.png

 

8bit_fig12_20_fa_sds_f16_lvs.png

 

This concluded the requirements for lab 7.  I have included a zipped file of the library here.

 

 

 

 

 

 

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