Lab 6 - ECE 421L 

Authored by Staford Snow, snows4@unlv.nevada.edu

10/26/2016

  

Lab description: In this lab, I drafted schematics, created symbols, designed layouts, and simulated a 2-input NAND and XOR gate using 6u/0.6u MOSFETs.  Following the completion of the gates, I drafted a schematic, created a symbol, designed a layout, and simulated a full adder circuit using my gates.

 

Pre Lab: Following the lab instruction, I backed up all my work from the lab and the course.  I next went through the instruction in Tutorial 4.

 

Lab:

 

To begin the lab, I drafted the schematics for the 2-input NAND and XOR gates using 6u/0.6u MOSFETS. 

 

nand_schematic.png  

 

After creating the schematics, I designed the symbols for both gates.

 

nand_symbol.png  xor_symbol.png

 

Continuing with the lab, I created the layout for the NAND and XOR gates.

 

nand_layout.png  xor_layout.png

 

I made sure both layouts passed LVS and DRC.

 

nand_drc.png  xor_drc.png

 

nand_lvs.png  xor_lvs.png

 

I next drafted a schematic to simulate my gates.  I included an inverter to increase my knowledge.

 

sim_schematic.png

 

I ran the simulation and was able to see that the timing of the input pulses caused glitches.  These glitches are cause, in part, by propagation delay through the gates.

 

sim_graph.png

 

After completing the NAND and XOR gate, I drafted the schematic for a full adder using the new gates.

 

fulladder_schematic.png

 

After completing the schematic, I created a symbol for this cell.

 

fulladder_symbol.png

 

Once I had the symbol completed, I used it in a schematic to run simulations.

 

sim_fulladder_schematic.png

 

I ran the simulation and was able to see the schematic working.

 

sim_fulladder_graph.png

 

I next designed a layout for the full adder using the gates I made earlier.

 

fulladder_layout.png

 

The layout passed DRC and LVS. 

 

fulladder_drc.png

 

fulladder_lvs.png

 

I have included my zipped library here.

 

This concluded the requirements of lab 6. 

 

 

 

 

 

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