Lab 5 - ECE 421L
Authored
by Staford Snow, snows4@unlv.nevada.edu
10/05/2016
Lab
description: In this lab, I drafted schematics, symbols and layouts of
two inverters each of size 12u/6u and 48u/24u. I then simulated
both with varying sizes of capacitance loads.
Pre
Lab: Following the lab instruction, I backed up all my work from
the lab and course. I then went through Tutorial 3 found here.
Lab:
To begin the lab, I drafted the schematic of 12u/6u and 48u/24u inverters. The 48u/24u inverter used a multiplier of m = 4.
I then created symbols for these schematics.
Following the creation of the symbols. I drafted the layout for each inverter.
Both layout passed DRC and LVS.
As per the lab instructions, I zippped the directory. It is available here.
Following the design of the inverters, I drafted schematics to simulate both.
I ran SPICE simulations for the schematics while adjusting the capacitive load.
I ran a simulation with a 100fF load:
1pF load:
10pF load:
100pF load:
Viewing
these results, as the load increases, the delay increases. When
the size of the NMOS and PMOS device increases, the delay decreases
proportionally.
I next used UltraSim to simulate the schematics.
I ran the UltraSim with a 100fF load:
1pF load:
10pF load:
100pF load:
This concluded the instruction of lab 5.
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