Lab 5 - ECE 421L 

Authored by Staford Snow, snows4@unlv.nevada.edu

10/05/2016

  

Lab description: In this lab, I drafted schematics, symbols and layouts of two inverters each of size 12u/6u and 48u/24u.  I then simulated both with varying sizes of capacitance loads.

 

Pre Lab:  Following the lab instruction, I backed up all my work from the lab and course.  I then went through Tutorial 3 found here.

 

Lab:

 

To begin the lab, I drafted the schematic of 12u/6u and 48u/24u inverters.  The 48u/24u inverter used a multiplier of m = 4.

 

inverter_schematic.png  inverter_m4_schematic.png

 

I then created symbols for these schematics.

 

inverter_symbol.png  inverter_m4_symbol.png

 

Following the creation of the symbols.  I drafted the layout for each inverter.

 

inverter_layout.png  inverter_m4_layout.png

 

Both layout passed DRC and LVS.

 

inverter_drc.png  inverter_m4_drc.png

 

inverter_lvs.png  inverter_m4_lvs.png

 

As per the lab instructions, I zippped the directory.  It is available here.

 

Following the design of the inverters, I drafted schematics to simulate both.

 

sim_inverter_schematic.png  sim_inverter_m4_schematic.png

 

I ran SPICE simulations for the schematics while adjusting the capacitive load.

 

sim_inverter_analysis.png  sim_inverter_m4_analysis.png

 

I ran a simulation with a 100fF load:

 

sim_inverter_100f.png  sim_inverter_m4_100f.png

 

1pF load:

 

sim_inverter_1p.png  sim_inverter_m4_1p.png

 

10pF load:

 

sim_inverter_10p.png  sim_inverter_m4_10p.png

 

100pF load:

 

sim_inverter_100p.png  sim_inverter_100p.png

 

Viewing these results, as the load increases, the delay increases.  When the size of the NMOS and PMOS device increases, the delay decreases proportionally.

 

I next used UltraSim to simulate the schematics.

 

ultrasim_inverter_analysis.png  ultrasim_inverter_m4_analysis.png

 

I ran the UltraSim with a 100fF load:

 

ultrasim_inverter_100f.png  ultrasim_inverter_m4_100f.png

 

1pF load:

 

ultrasim_inverter_1p.png  ultrasim_inverter_m4_1p.png

 

10pF load:

 

ultrasim_inverter_10p.png  ultrasim_inverter_m4_10p.png

 

100pF load:

 

ultrasim_inverter_100p.png  ultrasim_inverter_m4_100p.png

 

This concluded the instruction of lab 5.

 

 

 

 

 

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