Lab 4 - ECE 421L 

Authored by Staford Snow, snows4@unlv.nevada.edu

09/28/2016

  

Lab description:  In this lab, we created schematics and layouts of NMOS and PMOS devices by following Tutorial 2.

 

Prelab:
 
Following the prelab instructions, I backed up my work completed Tutorial 2.
 
Lab:
 
We began the lab by generating a schematic for a NMOS device with a 6u/600n width-to-length ratio.
 
nmos_schematic.png
 
I used this schematic to make the symbol used for simulating the NMOS.
 
nmos_sim_schematic.pngnmos_sim_schematic.png
 
I configured the ADE L to graph ID vs VDS while carying VGS from 0v to 5v in 1V steps while varying VDS from 0v to 5V in 1mV steps.
 
nmos_id_v_vds_graph_setup.png
 
That produced the following relationship:
 
nmos_id_v_vds_graph.png
 
I then configured the ADE L to graph ID vs VGS while varying VGS from 0V to 2V in 1mV steps while VDS is set to 100mV.
 
nmos_id_v_vgs_graph_setup.png
 
Which produce the this relationship:
 
nmos_id_v_vgs_graph.png
 
I next generated the schematic for a PMOS device with a 12u/600n width-to-lenght ratio.
 
pmos_schematic.png
 
I used that schematic to create the symbol I used in the following PMOS simulation circuit.
 
pmos_sim_schematic.png
 
I next configured the ADE L to plot ID vs VSD while varying VSG from 0V to 5V in 1V steps and varying VSD from 0V to 5V in 1mV steps.
 
pmos_id_v_vsd_graph_setup.png
 
That provided the following graphical representation:
 
pmos_id_v_vsd_graph.png
 
Following that output, I configured the ADE L to plot ID vs VSG while VSD is set to 100mV and varying VSG from 0V to 2V in 1mv increments.
 
pmos_id_v_vsg_graph_setup.png
 
Which produced the following graph:
 
pmos_id_v_vsg_graph.png
 
The lab next instructed me to create a layout of a 6u/600n NMOS device and connecting all 4 MOSFET terminals to probe pads.
 
nmos_layout_1.png
 
nmos_layout_2.png
 
I verified the layout passed the DRC.
 
nmos_drc.png
 
Finally verifying it passes LVS in comparison to the schematic.
 
nmos_lvs.png
 
Next I created a layout for a 12u/600n PMOS device with all 4 MOSFET terminals connected to probe pads.
 
pmos_layout_1.png
 
pmos_layout_2.png
 
I verified the PMOS device passed the DRC.
 
pmos_drc.png
 
And verified LVS passed against the schematic.
 
pmos_lvs.png
 
This concluded the instruction of the lab.

 

 

 

 

 

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