Lab 4 - ECE 421L
Authored
by Staford Snow, snows4@unlv.nevada.edu
09/28/2016
Lab
description: In this lab, we created schematics and layouts of NMOS and PMOS devices by following Tutorial 2.
Prelab:
Following the prelab instructions, I backed up my work completed Tutorial 2.
Lab:
We began the lab by generating a schematic for a NMOS device with a 6u/600n width-to-length ratio.

I used this schematic to make the symbol used for simulating the NMOS.

I
configured the ADE L to graph ID vs VDS while carying VGS from 0v to 5v
in 1V steps while varying VDS from 0v to 5V in 1mV steps.

That produced the following relationship:

I then configured the ADE L to graph ID vs VGS while varying VGS from 0V to 2V in 1mV steps while VDS is set to 100mV.

Which produce the this relationship:

I next generated the schematic for a PMOS device with a 12u/600n width-to-lenght ratio.

I used that schematic to create the symbol I used in the following PMOS simulation circuit.

I
next configured the ADE L to plot ID vs VSD while varying VSG from 0V
to 5V in 1V steps and varying VSD from 0V to 5V in 1mV steps.

That provided the following graphical representation:

Following
that output, I configured the ADE L to plot ID vs VSG while VSD is set
to 100mV and varying VSG from 0V to 2V in 1mv increments.

Which produced the following graph:

The lab next instructed me to create a layout of a 6u/600n NMOS device and connecting all 4 MOSFET terminals to probe pads.


I verified the layout passed the DRC.

Finally verifying it passes LVS in comparison to the schematic.

Next I created a layout for a 12u/600n PMOS device with all 4 MOSFET terminals connected to probe pads.


I verified the PMOS device passed the DRC.

And verified LVS passed against the schematic.

This concluded the instruction of the lab.
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