Lab 2 - ECE 421L 

Authored by Staford Snow, snows4@unlv.nevada.edu

09/14/2016

  

Lab description: In this lab, I designed and simulated a 10-bit DAC using 10k resistors.  I learned how to create a symbol from a schematic and use it in a different design.

 

Prelab:

 

After following the prelab instructions provided here, I was able to add the lab2 design directory to Cadence.

 

I then lanched Cadence and navigated to the lab2 library.

 

prelab_setup.jpg

 

Upon opening the schematic view of the sim_Ideal_ADC_DAC cell, I observed the Ideal ADC to DAC schematic.

 

prelab_schematic.jpg

 

Finally, I lanched the ADE L to run a transient analysis and examine the output graph.

 

prelab_graph.jpg

 

Lab:

 

The lab began by instructing us to design a 10-bit DAC using an n-well R of 10k.  Using this image as a guide, I created the following 10-bit DAC out of 10k resistors.

 

dac_schematic.jpg

 

Calculating the output resistance of the DAC gives us a value of 10kΩ.  To calculate this value, I started at the bottom ground node and found the series resistance to the next node, 20kΩ.  This equivalent resistanceis parallel to the next branch resistance of 20kΩ, which gives a new equivalent resistance of 10kΩ.  Continuing this process "up" the schematic gives the final equivalent resistance of 10kΩ.

 

I then converted this schematic into a symbol to ease in use for future applications by following the instructions in Tutorial 1.

 

dac_symbol.jpg

 

After creating the symbol, I predicted the delay of the DAC while driving a 10pF load.  The equation I used was td≈0.7RC.

Substituting the equivalent resistance and load capacitance, td≈0.7*10kΩ*10pF => td≈70ns.

I verified this by creating this simple circuit.

 

delay_schematic.jpg

 

After running a transient analysis, I was able to confirm my prediction.  Taking into account the 10ns delay of the voltage source.

   

delay_graph.jpg

 

Following the creation of the symbol for my DAC, I substituted it into the original  sim_Ideal_ADC_DAC.

 

sim2_schematic.png

 

Running a transient analysis using ADE L, I observed the graphical output.

 

sim2_graph.png

 

I implemeted that circuit driving R, C, and RC loads.

 

sim2_10k_schematic.png

 

sim2_10p_schematic.png

 

sim2_10k_10p_schematic.png

 

Using ADE L, I ran transient analyses to observer how each load effected the output.

 

Using a load of 10kΩ, the output voltage is reduced by 50%.  This is because with a 10kΩ resistance in series with the equivalent resistance of the DAC equates to 20kΩ.  The 5V input has double the voltage drop, creating an output reduction of 50%.

 

sim2_10k_graph.png

 

Using a load of 10pF, I observed the following graphical output.

 

sim2_10p_graph.png

 

Combining these loads into, the following was presented graphically.

 

sim2_10k_10p_graph.png

 

One thing to note; in a real circuit, the switches shown in the design guide are the outputs of the ADC.  These are implemented with MOSFET transistors.  The resistance of these transistors must be small in relationship to my R of 10kΩ.  If the transistors resistance is close to, equal, or larger than my DAC's equivalent resistance, the input resistance to the DAC will alter the output voltage.  This can give inaccurate results, which can cause problems in the real world.

 

Following these graphical representations in different load scenarios, I reverted to a loadless DAC to observe the effect of lowering the convergence values.

 

sim2_converge.jpg

 

Running the simulation again with these values resulted in a less accurate graphical representation of the output.

 

sim2_converge_graph.jpg

 

This concluded lab 2.

 

 

 

 

 

 

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