EE 421L Digital Integrated Circuit Design Laboratory - Lab
6
10/26/16
Pre-lab
o Back-up all of your work from
the lab and the course.
o Go through Cadence Tutorial
4
o Read through the lab in its
entirety before starting to work on it
Draft
the schematics of a 2-input NAND gate (Fig. 12.1), and a 2-input XOR gate (Fig.
12.18) using 6u/0.6u MOSFETs (both NMOS and PMOS)
o Create layout and symbol views
for these gates showing that the cells DRC and LVS without errors
o ensure that your symbol views
are the commonly used symbols (not boxes!) for these gates with your initials
in the middle of the symbol
o ensure all layouts in this lab use
standard cell frames that snap together end-to-end for routing vdd! and gnd!
o use a standard cell height
taller than you need for these gates so that it can be used for more
complicated layouts in the future
o ensure gate inputs, outputs, vdd!, and gnd! are all routed on
metal1
o Use cell names that include
your initials and the current year/semester, e.g. NAND_jb_f19 (if it were fall
2019)
o Using Spectre
simulate the logical operation of the gates for all 4 possible inputs (00, 01,
10, and 11)
o comment on how timing of the
input pulses can cause glitches in the output of a gate
o Your html lab report should
detail each of these efforts
Below
shows (click for a larger image): 1) schematic of a 2-input NAND gate, 2)
schematic of a 2-input XOR gate, 3) simulation schematic, 4) example pulse
statement to generate a digital input, and 5) simulating the operation of the
gates for all 4 possible inputs.
Experiment 1:
2-Input NAND Gate and 2-Input XOR Gate
The
first step in Laboratory 6 was the creation of 2-Input (2 I/P) NAND gate and 2
I/P XOR gate schematic, symbol, and layout views, found in the files NAND_EM_f16 and XOR_EM_f16, respectively. The designs use 6µ/0.6µ MOSFETS as
required in the laboratory instructions. First, the 2 I/P NAND schematic with
successful DRC verification is displayed below.
Next,
the symbol for the 2 I/P NAND with DRC verification is
displayed below. Note the initials 'EM' in the center of the symbol as directed
in the laboratory instructions.
Following
the symbol, the 2 I/P NAND layout was created with
successful DRC and LVS verification. Additional spacing was left between the
PMOS and NMOS to allow space for routing in more complex designs, as well as to
allow routing for the FULL ADDER (FA) in this laboratory experiment. Note, all
I/P's, outputs (O/P's), vdd! and
gnd! are routed on metal1.
The layout with DRC verification is displayed below.
The
extracted 2 I/P NAND with LVS verification is
displayed below.
Moving
on, the 2 I/P XOR schematic design with successful DRC verification is
displayed below. The 2 I/P XOR files used are found in the file XOR_EM_f16.
Next,
the 2 I/P XOR symbol with initials in the center was designed as displayed below.
The
layout for the 2 I/P XOR required careful attention to routing transmission
lines due to the complexity of the design relative to design experience.
Initially, the crossing of metal1 (m1) and metal2 (m2) presented difficulty. The
original design included both m1 and m2 running both horizontally and
vertically. This approach was successful for the 2 I/P XOR alone, however the
approach made connecting the XOR with other components, as seen later in the FA
design, more complicated and relatively messy. Thus, the initial design was
reconstructed using the approach suggested in the CMOS Circuit Design, Layout and
Simulation book , specifically using a grid pattern to route the metal layers.
Although, there are instances where this approach was violated, the net result
was a cleaner design. Note, all I/P's, outputs (O/P's), vdd!, and gnd! are
routed on metal1.The layout with DRC verification prior to redesigning is
displayed below.
For
comparison, the redesigned 2 I/P XOR used in the FA is displayed below. Note,
most of the long vertical connections were made using m1 and the horizontal
connections were made using m2. The instances where this strategy was violated
are the connections to vdd!,
gnd!, and a connection between two PMOS drains.
Next,
the 2 I/P XOR extracted view with LVS verification is displayed below.
Following
design completion, Spectre was used to simulate the
logical operations of the gates for the 4 possible I/P combinations. To
simplify, one schematic was used, as displayed below. The schematic and saved Spectre state are found in the
file sim_NAND_XOR_EM_f16.
The
simulation was performed with the following pulse inputs for A, below left, and
B, below right, to provide the 4 possible input combinations. Note B has a
period one-half the period of A.
Prior
to providing the simulation results, the truth tables for each design are
included for reference. The simulation results for the schematic are displayed
below the table. Reading the signals vertically from right to left on the plot
confirms the simulations results match the truth tables.
|
A |
B |
AnandB |
AxorB |
|
0 |
0 |
1 |
0 |
|
0 |
1 |
1 |
1 |
|
1 |
0 |
1 |
1 |
|
1 |
1 |
0 |
0 |
To
verify the layouts were designed properly, the same simulation was performed
using the extracted view. The plot below displays the same simulation using the
extracted layout. Note the simulation results are identical.
The
netlists for the simulation results are displayed for the schematic, below
left, and the extracted view, below right.
Experiment 2:
Full Adder
Using
these gates, draft the schematic of the full adder seen below
o Create a symbol for this
full-adder
o Simulate, using Spectre, the operation of the full-adder using this
symbol
Layout
the full-adder by placing the 5 gates end-to-end so that vdd!
and gnd! are
routed
o full-adder inputs and outputs
can be on metal2 but not metal3
DRC
and LVS your full adder design
The 2 I/P NAND and the 2 I/P XOR designed in Experiment 1 were
connected in the Full Adder design seen above. The schematic with DRC
verification is displayed below. The design file used for this experiment is
titled FA_EM_f16.
Following the schematic design, the commonly used FA symbol was
designed. The symbol with DRC verification is displayed below. Again, note the
initials displayed in the center of the symbol, as required.
The layout of the FA initially presented difficulties routing m1
and m2, as noted in the discussion for the 2 I/P XOR gate. Additionally, metal3
(m3) was used for part of the layout. The first attempt at the FA resulted in a
layout with the 2 XOR's and the 3 NAND's connected successively in a row from left
to right. The layout resulted with metal
layers and connections in an unsatisfactoryf design.
However, after considering several design strategies and analyzing the input
and output locations on both devices, the FA layout was completed by
rearranging the order of the connected components and using the metal layout
strategy discussed earlier. Laying the metal out in a grid avoided the problem
of routing metal layers across themselves horizontally and vertically and
resulted in a satisfactory layout for the FA. Note the layout with successful
DRC verification below. Also, note none of the FA I/P's or O/P's are on m3.
Next, a closer view of the completed
FA.
The final step of the FA design was to extract and LVS the design.
The initial LVS failed due to failure to add the proper input pin for 'Cin' and output pin for 'S'. Once these were added, the LVS
was successful, as displayed below.
The final part of Experiment 2 was to simulate the FA using the
symbol. This was performed using both the schematic and extracted views. The
simulation file and saved Spectre state can be found
in the file sim_FA_EM_f16. The image
below displays the schematic with DRC verification used for the simulation.
The inputs required to perform the simulations are displayed below
from left to right for A, B and cin, respectively.
The A and B inputs are the same, with the period for cin
being one-half of B or one-fourth of A. This results in all 8 possible I/P
combinations.
As done previously, the truth table for the FA is displayed below.
The simulation results using the schematic symbol are displayed directly below
the truth table. The truth table can be read directly from the simulation
results reading vertically from right to left.
|
A |
B |
cin |
S |
cout |
|
0 |
0 |
0 |
0 |
0 |
|
0 |
0 |
1 |
1 |
0 |
|
0 |
1 |
0 |
1 |
0 |
|
0 |
1 |
1 |
0 |
1 |
|
1 |
0 |
0 |
1 |
0 |
|
1 |
0 |
1 |
0 |
1 |
|
1 |
1 |
0 |
0 |
1 |
|
1 |
1 |
1 |
1 |
1 |
The Spectre simulation results for the
extracted layout are displayed below. The results confirm the layout is
designed correctly. Below the simulation results are the netlists for the
schematic simulation, left, and the extracted simulation, right.
Conclusion
The experiments performed in Laboratory 6 resulted in the design
of a 2-input NAND gate, a 2-input XOR gate and a Full Adder using familiar
devices from previous laboratory experiments, specifically NMOS and PMOS
transistors. Additionally, the devices were successfully simulated using both
schematic and extracted views to verify proper functionality.
Return to
Monahan Lab Report Directory
Return to EE 421L
Fall 2016 Student Directory