EE 421L Digital Integrated Circuit Design Laboratory - Lab
3
9/21/16
Layout
of a 10-bit DAC
Pre-Lab
o Back-up all of your previous
work from the lab and the course.
o Finish Tutorial 1
Tutorial 1 was completed with files
relevant to Lab 3 included in the DAC layout. The images below are samples of
the 10kΩ resistor, left, and the voltage divider, right, from the
Tutorial.
The DRC and LVS verifications for the
Tutorial 1 voltage divider are displayed below. Completing the tutorial was
relevant to completing the layout of the 10-bit DAC in the following
experiment.
Experiment
1
This
lab will focus on the layout of the 10-bit DAC you designed and simulated in Lab
2
Use
the n-well to layout a 10k resistor as discussed in Tutorial 1
o Discuss, in your lab report, how
to select the width and length of the resistor by referencing the process
information from MOSIS
First, all files created in Lab 2
were copied to the Lab 3 library to simplify the design process required in
this experiment.
Next, the length and width of the
resistor needed to be determined to meet the parameters specified in the MOSIS
design rules. The design rules specify the sheet resistance at 800Ω/square
and the minimum length as 3.6µm. The mathematical relationships displayed in
the image below are used to determine the length and width. As demonstrated in
Tutorial 1, a width of 4.5µm was used and the length was determined as
demonstrated below.
Once the theoretical length was
determined to result in the desired 10kΩ n-well resistor, the experimental
design process demonstrated in Tutorial 1 was performed to create the resistor.
The finished resistor is displayed directly below. Note the ruler displayed
demonstrating the length and width matching the theoretically calculated
values. For reference, the ruler is accessed via the 'k' Bindkey.
The extracted view of the ruler is
displayed below.
The final value of the resistor is
displayed on the extracted view. Note the resistor value is 10.21kΩ,
representing an acceptable approximation of the desired 10kΩ initially
derived above.
Experiment
2
Use
this n-well resistor in the layout of your DAC
o Discuss, in your lab report,
how the width and length of the resistor are measured
·
Ensure
that each resistor in the DAC is laid out in parallel having the same
x-position but varying y-positions (the resistors are stacked)
·
All
input and output Pins should be on metal 1
·
DRC
and LVS, with the extracted layout, your design (show the results in your lab report)
·
Zip
up your final design directory and place it in the lab3 directory, with a link
on your lab report, so the grader can examine both the layout and
schematic (and simulations)
The
layout of the DAC began with the creation of a layout for a 1-bit DAC. The
1-bit DAC schematic designed in Lab2 displayed below to the left,
was used for the layout reference. The layout is displayed below to the
right.
The extracted layout is displayed below.
The image below is the DRC for the layout verifying no design rule
errors. Below the DRC image is an image of the LVS verifying net-lists match
for the schematic and extract.
The next step was the design of the stacked 10-bit DAC via the
1-bit DAC designed above. The resistors were stacked in parallel with the same
x-positions and varying y-positions. The image to the left below displays the
10-bit DAC layout and the image to the right displays the extracted view. The
middle image displays a closer view of the layout to provide a sample of the
Pin naming conventions used in the design.
The image to the left below is the 10-bit DAC layout DRC
displaying no errors and the image to the right displays the LVS verifying
matching net-lists.
Experiment
3
The
final experiment required repeating the simulations performed in Lab
2 using the ADC_DAC file with the extracted file created above. To simulate
using the extracted file, the same schematics were used with changes made in the
ADE L prior to simulating. Specifically, the following steps were taken:
o
In the ADE, click Setup >
Environment and add the word extracted to the file
o
Load the Session and simulate
o
In the ADE, click Simulation
> Netlist > Display
The
first and last steps are displayed below. The netlist view confirms the
extracted file is used for the DAC in the simulations.
The
first simulation performed was under no load conditions as done in Lab2. This
used the file sim_ECM_ADC_DAC in the Lab_3
library. The images below display
simulation results for the schematic DAC, left, and the extracted DAC, right.
All remaining simulation and netlist images will follow the format of schematic
DAC sim on the left next to the extracted DAC sim on the right. The simulations
produced identical results. The netlists for each are seen directly below the
plots.
The
next simulation was for the DAC connected to a 10pF load using the file
sim2_DAC_C_load in the Lab_3 library. The resulting simulations and netlists
are seen below. Once again, the simulations produced identical results.
Next,
the DAC was connected to drive varying loads (R, C and R/C) as previously done
in Lab 2. First, a 10kΩ load was added and simulated using the file
sim_ECM_DAC_10k_load with results displayed below. The results show a 2.5V amplitude for a 5V pulse, as seen in the initial
plot. Thus, identical results once again.
The
next simulation used the file sim_ECM_DAC_10pF_load and replaced the 10kΩ
resistor above with a 10pF capacitor. Simulation results are displayed below.
Once again, the simulations for the schematic DAC and the extracted DAC
match.
Finally,
a simulation was performed with the DAC driving a 10kΩ resistor and a
10pF capacitor using the file sim_ECM_DAC_RC_load.
Simulation results are displayed below.
As
demonstrated above, the simulation results using the schematic DAC versus the
extracted layout DAC are identical.
Conclusion
The
layout of a 10-bit DAC performed in Laboratory 3 served as an extension of the
experiments performed in Lab 2. Specifically, the 10-bit DAC schematic designed
in Lab 2 was given a layout, extracted and simulated as done in Lab 2.
Performing the simulations using the extracted DAC required additional research
into Cadence simulations, but the simulations were performed as expected. As in
Lab 2, the simulation results using the extracted 10-bit DAC matched the
expected outcomes for the load conditions simulated.
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