EE 421L Digital Integrated Circuit Design
Laboratory - Lab 2
9/7/16
Design of a 10-bit digital-to-analog converter (DAC)
Pre-lab
- Back-up
all of your work from the lab and the course.
- Read
through this entire lab write-up before doing the pre-lab
- Download
lab2.zip to your desktop.
- This archive contains a simulation example using an
ideal 10-bit Analog-to-Digital Converter (ADC)
and Digital-to-Analog Converter (DAC).
- Upload
this zip file to the design directory on the server that you are running
Cadence from, e.g., Tutorial_1, CMOSedu, etc.
- Note that it's assumed you are using the NCSU Cadence
Design Kits.
- Unzip
this directory and add, to your cds.lib in the design directory, the
following statement (assuming the design directory is CMOSedu):
- DEFINE lab2 $HOME/CMOSedu/lab2
- Start
Cadence from the design directory.
- Use the Library Manager and navigate to the lab2
Library as seen below.
- Open
the schematic view of the cell sim_Ideal_ADC_DAC.
- This cell contains the ideal 10-bit ADC and DAC as
seen below in the second image.
Prior
to coming to lab make sure you understand how the input voltage, Vin, is
related to B[9:0] and Vout
(the quiz may ask a question about this).
The input voltage, Vin,
represents a continuous analog input to the analog-to-digital converter (ADC).
The ADC compares the input signal to a reference voltage divider network that
utilizes comparators dependent upon the input voltage to switch on or off. The
result is the conversion of the analog signal to the discrete time, 10-bit
digital signal, B[9:0]. Essentially, the ADC receives
an analog signal, such as a sine wave, and converts the signal to a digital
signal, represented by bits. In this laboratory experiment, signal B has ten
inputs with each input having two possible states, 0 or 1. This signal results in 1024 possible binary
combinations, as demonstrated below.
The converted analog signal B then
enters a digital-to-analog converter (DAC) composed of a resistive ladder
network with transistors acting as switches. The switches convert the digital
signal B back to a discrete time signal, Vout.
Thus, Vout represents the analog version
of the digital signal B created in the ADC.
Prelab
Experiment 1: Provide a narrative of the steps seen above.
The initial portion of the
prelab required downloading the lab2.zip file, uploading the file to the CMOSedu design directory and extracting the file contents.
This is demonstrated in the image to the left below. Next, " DEFINE lab2 $HOME/CMOSedu/lab2"
was added to the cds.lib file, as displayed to the right below, to point
Cadence to the proper files for the DAC/ADC simulations required for the
experiment.
Next, the schematic view of the cell sim_Ideal_ADC_DAC was opened via the library manager and
simulated in the ADE by loading in the previously saved state included in the
lab2 file. The image directly below displays the Library Manager with the
properly selected file.
The image to the left
below displays the sim_Ideal_ADC_DAC schematic and
the image to the right below displays the simulation result prior to altering
the original circuit. The traces for the input and output signals were changed
to solid red (input) and solid blue (output) and the default background of the
schematic was changed to white by following suggestions from the CMOSedu Cadence tutorials. An alternate simulation will be
executed and detailed below.
Prelab
Experiment 2: Provide and discuss simulation results
different from the above to illustrate your understanding of the ADC and DAC.
As
previously discussed, the ADC converts an analog signal to a digital signal and
the DAC converts a digital signal to analog. The results seen above were
obtained using the values initially set in the sim_Ideal_ADC_DAC schematic. The supply
powering the circuit, Vdd, ranges from 0V
to 5V. Thus, the output signal is limited to this range. This is demonstrated
in the images displayed below. The left image displays the initial values for
source V4 and the image to the right displays the altered amplitude,
Va. The image below these displays the ADE
L simulation results where the output signal is clearly clipping. This is due
to the analog input signal exceeding the range of the 10-bit DAC. The DAC is
limited by the supply voltage and number of bits, thus the clipping is
present.
Prelab
Experiment 3: Explain how you determine the
least significant bit (LSB, the minimum voltage change on the ADC's input to
see a change in the digital code B[9:0]) of the
converter. Use simulations to support your understanding.
To
determine the LSB, the supply voltage Vdd
can be divided by the number of possible binary words. As previously
calculated, the number of possible binary words for this experiment is 1024.
The results are displayed below.
The
result is 1-bit digitally represents 4.88mV. The plot below represents a
simulation performed with the initial input values from the lab2 file. The
green plot represents B9, the most significant bit (MSB). This value is
determined by multiplying the LSB by the total number of possible binary words,
4.88mV*1024, resulting in 4.997V, a digital output approximating the peak
analog output. The LSB, B0, is represented by the blue line.
Experiment
1
Design
of a 10-bit DAC using an n-well R of 10k
o The 2R resistor should be implement with two separate 10k resistors in series.
o After you've designed and
drafted your schematic check and save it.
o Create a symbol view for your design
with the exact same footprint as the Ideal_10-bit_DAC symbol view.
Simulations
to verify your design functions correctly.
o Copy the schematic cell view sim_Ideal_ADC_DAC to a cell sim2_Ideal_ADC_DAC and replace
the ideal DAC with the one you just designed.
o Use the sim2_Ideal_ADC_DAC to
illustrate that your design works as expected.
First, a voltage divider schematic
was designed using only 10kΩ resistors with pins and nodes named
appropriately. This was converted into a symbol to function in the ladder
network required in the DAC design. The schematic and symbol images are
displayed below to the left and right, respectively.
After creating the 1-bit DAC above,
the 10-bit DAC was designed by connecting 10 1-bit DAC's together. This
resulted in some initial design errors caused by routing connections
incorrectly and proved time consuming despite the simplicity of the design. The
10-bit DAC schematic and symbol are displayed below to the left and right,
respectively. Note the symbol has the same footprint as the ideal DAC.
The next step involved replacing the
DAC in the sim_Ideal_ADC_DAC schematic with the 10-bit DAC designed above.
The altered schematic is displayed below.
The images below compare the plot from the original ideal DAC, below
left, to the plot obtained with the experimentally designed DAC, below right,
seen above. The results demonstrate the experimentally designed DAC closely
approximates the ideal DAC. Note both outputs peak just short of the 5V analog
signal at 4.997V. as previously calculated.
Experiment
2
Show
how to determine the output resistance of the DAC (answer: R) by combining
resistors in parallel and series.
To determine the output resistance of
the DAC, simple circuit analysis techniques are followed. An iterative process
of grounding all the bits and combining resistors in parallel and in series is
performed to simplify the DAC output resistance to 'R', or 10kΩ. This is
demonstrated in the image below.
Experiment
3
Delay,
driving a load
o Ground all DAC inputs except
B9. Connect B9 to a pulse source (0 to VDD) and show, and predict using 0.7RC,
the delay the DAC has driving a 10 pF load
o Verify the simulation results
match your hand calculations
Hand calculations predicting the time
delay of the DAC driving a 10pF load are displayed below. Recall the DAC
resistance was determined to be 10kΩ.
The schematic and ADE L simulation
results are displayed below to the left and right, respectively. The simulation
verifies the theoretical calculation determined above.
Show
what happens if the DAC you designed drives a load (both R,
C, and R/C). Explain what happens if the DAC drives a 10k load?
The simplest method to show what
happens if the DAC drives a load was to connect a 10kΩ load to the
output, thus creating a voltage divider. The result will be yet another voltage
divider due to the equivalent 10kΩ output resistance of the DAC. The 2.5V
output amplitude is approximately half the 5V input as expected.
Next a 10pF capacitor load replaced the 10kΩ resistor as
displayed in the image to the left below. The simulation results displayed to
the right below display a reduced amplitude and a
phase shift as expected.
The last load connected was an R/C load, as
displayed in the image to the left below. The simulation results for the R/C load
are displayed below to the right.
In
a real circuit the switches seen above (the outputs of the ADC) are implemented
with transistors (MOSFETs).
o Discuss what happens if the resistance of the switches isn't small compared to R.
If the resistance related to the
switches is not negligible compared to the DAC output resistance, R, loading
effects will impact the output thus resulting in a smaller than desired output
voltage. This effect is due to the voltage dropping across a higher resistance.
Conclusion
The experiments performed in
Laboratory 2 served to demonstrate the fundamental operation of both
analog-to-digital and digital-to-analog converters. Furthermore, the design of
a 10-bit DAC was realized and simulated under various load conditions with
theoretical and experimental results matching expected outcomes.
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